2014年6月12日 星期四

00 to 99 Two Digit Decimal Counter via 7 Segment Display Using Verilog

00 to 99 Two Digit Decimal Counter via 7 Segment Display Using Verilog 
源自於http://simplefpga.blogspot.co.uk/2012/07/00-to-99-two-digit-decimal-counter-via.html

reset ==> KEY[0]
HEX1:HEX0==>Data out 00-99


//適用於DE2-70 的程式
module two_digit_count(
 input [17:0]SW,
 input [3:0] KEY,
 input  CLOCK_50,

 output [17:0] LEDR,
 output [7:0] LEDG,
 output [6:0] HEX0,
 output [6:0] HEX1,
 output [6:0] HEX2,
 output [6:0] HEX3,
 output [6:0] HEX4,
 output [6:0] HEX5,
 output [6:0] HEX6,
 output [6:0] HEX7
 );

//assign HEX0=7'b111_1111;  //off 7-segment Display
//assign HEX1=7'b111_1111;
assign HEX2=7'b111_1111;
assign HEX3=7'b111_1111;
assign HEX4=7'b111_1111;
assign HEX5=7'b111_1111;
assign HEX6=7'b111_1111;
assign HEX7=7'b111_1111;
assign LEDR[17:0]=SW[17:0];  //SW status =>LEDR
wire [3:0] digit0,digit1;
wire clk_1hz;

//clk_div_1hz(clk_in , Reset, clk_out);
clk_div_1hz u1(CLOCK_50, KEY[0], clk_1hz);
main_two_digit_count u2(clk_1hz,KEY[0],digit0,digit1);
hex_7seg u3(digit0,HEX0);
hex_7seg u4(digit1,HEX1);

endmodule


module main_two_digit_count(
input clock_1hz,
    input reset,
    output reg [3:0] digit0,
    output reg [3:0] digit1
    );
   

always @ (posedge clock_1hz or negedge reset)
 begin
  if (!reset) begin
   digit0<=0;
   digit1<=0;
   end 
  
  else if (digit0>=4'd9)
  begin
    digit0<=0;     //0's ==0

if (digit1>=4'd9) //10's >9 ??
digit1<=0;       //10's==0
else 
digit1=digit1+1; //10's+1
   end
  else 
digit0=digit0+1; //0's+1
  
end
endmodule

 module hex_7seg(hex_digit,seg);
input [3:0] hex_digit;
output [6:0] seg;
reg [6:0] seg;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off

always @ (hex_digit)
case (hex_digit)
  4'h0: seg = 7'b1000000;
  4'h1: seg = 7'b1111001;  // ---a----
  4'h2: seg = 7'b0100100;  // |   |
  4'h3: seg = 7'b0110000;  // f   b
  4'h4: seg = 7'b0011001;  // |   |
  4'h5: seg = 7'b0010010;  // ---g----
  4'h6: seg = 7'b0000010;  // |   |
  4'h7: seg = 7'b1111000;  // e   c
  4'h8: seg = 7'b0000000;  // |   |
  4'h9: seg = 7'b0011000;  // ---d----
  4'ha: seg = 7'b0001000;
  4'hb: seg = 7'b0000011;
  4'hc: seg = 7'b1000110;
  4'hd: seg = 7'b0100001;
  4'he: seg = 7'b0000110;
  4'hf: seg = 7'b0001110;
endcase
endmodule

module clk_div_1hz(clk_in , Reset, clk_out);
input clk_in ;
input Reset;
output reg  clk_out;

integer i;
always@(posedge clk_in or negedge Reset) begin
 if (!Reset) begin
   i=0;
   clk_out=0;
   end
 else begin
    i= i+1 ;
    if (i>=24_999_999) begin
        clk_out  = ~clk_out;
        i=0;
       end
    end    
end            

endmodule





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