General syntax is as follows:
if( condition ) statement;if( hold == 0 ) counter = counter + 1;
if( reset )
counter = 0; else
counter = counter + 1;
if( reset )
begin
counter <= 0;
over_flow <= 0; end
else if ( counter == 15 ) begin
counter <= 0;
over_flow <= 1; end
else
begin
counter <= counter + 1;
over_flow <= 0;
end
begin
counter <= 0;
over_flow <= 0; end
else if ( counter == 15 ) begin
counter <= 0;
over_flow <= 1; end
else
begin
counter <= counter + 1;
over_flow <= 0;
end
if-else statements should be used inside initial or always blocks.
module addsub (a, b, addnsub, result); input[7:0] a; input[7:0] b; input addnsub; output[8:0] result; reg[8:0] result; always @(a or b or addnsub) begin if (addnsub) result = a + b; else result = a - b; end endmodule |
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