2014年6月3日 星期二

Verilog Data types

Data types in Verilog are divided in to nets and registers.  wire, tri, wor, trior, wand, triand, tri0, tri1, supply0, supply1 and trireg are net data types. reg, integer, time and real are register data types.

Net Data Types
wire is the most widely used net data type. It represents 1 bit interconnecting wire. 

wire identifier;

module wortest();

wor w1, w2, w3, w4;

assign w1 = 0;
assign w1 = 0;

assign w2 = 0;
assign w2 = 1;

assign w3 = 1;
assign w3 = 0;

assign w4 = 1;
assign w4 = 1;

initial
begin
    $display(w1, w2, w3, w4);
end

endmodule


In the following code, you can make out the difference between wire, tri0 and tri1.
module tritest();

wire w1, w2, w3, w4;
tri0 t01, t02, t03, t04;
tri1 t11, t12, t13, t14;

assign w1 = 0;
assign t01 = 0;
assign t11 = 0;

assign w2 = 1'bz;
assign t02 = 1'bz;
assign t12 = 1'bz;

assign w3 = 1;
assign t03 = 1;
assign t13 = 1;

initial
begin
  #1;
  $display(w1, w2, w3, w4);
  $display(t01, t02, t03, t04);
  $display(t11, t12, t13, t14);

end
endmodule
and the output will be as follows:
0z1z 0010 0111
supply0 and supply1 are tied to logic 0 and 1 respectively.
Register Data Types
reg is a single bit register data type. If a value is assigned to reg type of signal, value will retain until a new value is assigned. In verilog, a register data type need not represent a real hardware register. So, it need not be consisting of  a flip-flop. It just means that a signal that holds the value. Default value of an un-initialized reg is 'x' or undefined.
integer, time and real are other register type of datatypes. integer is a signed variable of 32 bits, time is unsigned integer, 64 bits and real is double precision floating point variable.

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