2014年6月7日 星期六

Blocking VS. Nonblcoking

 Blocking VS. Nonblcoking
源自於
http://blog.csdn.net/chevroletss/article/details/6305697


Blocking: ‘ = ’
Execution of blcoking assignments is a one-step process: Evaluate the right-hand side argument and update left-hand side argument of the blocking assignment without interruption from any other Verilog statement.
‘Blocking’ trailing assignments in the same always block from occuring until after current assignment has completed


Nonblocking: ’<=’
Execution of nonblocking assignments can be viewed as a two-step process:
1、Evaluate the right-hand side of nonblocking statements at the beginning of the time step
2、Update the left-hand side of nonblocking statements at the end of the time step
Allows assignment scheduling without blocking evaluation and execution of other Verilog statements
Only used in procedural blocks.


Blocking VS. Nonblcoking,
simualtion waves, synthezied results and Verilog code.

always @(posedge Clock)// negedge Reset) 
         begin 
            Data1_out = Data_in; 
            Data2_out = Data1_out;            
         end   



cannot synthesize to two flip-flops, two output connect with each other


always @(posedge Clock)// negedge Reset)
begin
   Data2_out = Data1_out;
  Data1_out = Data_in;
end







always @(posedge Clock)// negedge Reset)
begin
Data1_out <= Data_in;
Data2_out <= Data1_out;
end



always @(posedge Clock)// negedge Reset)
begin
  Data2_out <= Data1_out;
  Data1_out <= Data_in;
end



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