2014年6月11日 星期三

王國華 老師的 數位系統導論


http://cad6.csie.fju.edu.tw/digital99/experiment.htm   王國華 老師


實 驗 課 進 度 表

 
週次日期實驗名稱
預定進度
教材學期分數
比例
書面
繳交期限
12/14, 2/18Lab 0: Logic Schematic
Introduction of Quartus II Design Flow Using Schematic
8%(乙),(甲)
22/21, 2/25Lab 0: Verilog Tutorial
Design Flow Using Verilog Hardware Description Language
3/1 , 3/4
32/28, 3/4Lab 1:  四位元加/減法器 (1/3)
Half-Adder, Full-Adder, 4-bit Adder
Component Design Using Current Design
Bus Design
4-bit Adder Component Design and Functional Simulation
13%
43/7,3/11Lab 1:  四位元加/減法器 (2/3)
4-bit Adder/Subtractor & its Functional Simulation
Top-Level Logic Circuit 
Download of 4-bit Adder/Subtractor (Schematic)
4-bit Adder/Subtractor
如何匯入外部元件 
seg7.v 
4-bit Adder/Sub上層設定
如何匯入Pin_Assignment
DE2-70 896
DE2 672
53/14,3/18Lab 1:  四位元加/減法器 (3/3)
Download of 4-bit Adder/Subtractor (Verilog)
4-bit Adder/SubtractorTop3/21,3/25
63/21,3/25Lab 2:  八位元比較器 (1/2)
1-bit, 2-bit, 4-bit , and 8-bit Comparators (Schematic)
Functional Simulation of All Components
Download of 8-bit Comparator (Schematic)
8-bit Comparators8-bit Comparators TOP10%
73/28, 4/1Lab 2:  八位元比較器( 2/2)
1-bit, 2-bit, 4-bit Comparators (Verilog)
Functional Simulation of All Components
Download of 8-bit Comparator (Verilog)
8-bit Comparator (Verilog)
4/ 7,4/8
84/4, 4/8Lab 3:  四位元乘法器 (1/2)
Download of 4-bit Multiplier
(Verilog using Structural & Dataflow Modeling)
Array-Multiplier-partMultiplier Top12% 
94/11, 4/15Lab 3:  四位元乘法器 (2/2)
Download of 4-bit Multiplier
(Verilog using 
generate statements)
nbit-Multiplier-Generate4/18,4/22
104/18,4/22期中上機考 (1)期中上機考 (1) 12% 
114/25,4/29期中上機考 (2)期中上機考 (2)  
125/2,5/6Lab 4: Simulation of Flop-Flops
Functional Simulation of JK, D, and T Flip-Flops
Flip-Flops6% 
135/9,5/13Lab 5:  Sequence Counter
Design of Sequence Counter using Verilog
Functional Simulation of Sequence Counter (Verilog)Download of Sequence Counter
Sequence Counter-二乙6% 
145/16,5/20Lab 6:  Analysis of Sequential Circuit
Functional Simulation of Sequential Circuits
Analysis of Sequential CircuitsLibrary Parameter Modules
Using LPMs
6% 
155/23,5/27Lab 7:  One's Bit Counter (1/2)
Design of Control Unit and Datapath
Veilog Code of One's Bit Counter
Functional Simulation of One's Bit Counter
One's Bit Counter12% 
165/30,6/3Lab 7:  One's Bit Counter (2/2)
Download of One's Bit Counter
  
176/6,6/10Lab 8:  Multiplier (1/2)
Design of Control Unit and Datapath
Veilog Code of Multiplier
Functional Simulation of  Multiplier
Multiplier15% 
186/13,6/17Lab 8:  Multiplier (2/2)
Download of Multiplier
甲班小考下載 
期末專題
(Optional)
6/20 Divider
Design of Control Unit and Datapath
Veilog Code of Divider
Functional Simulation of  Divider

Download of 
Enhance Divider
Divider12% 

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