利用2-4解碼器擴充到4-16解碼器---適用於DE2-70 (由50MHz轉成1HZ 再送至16模計數器)

CD74HC4514  High Speed CMOS Logic 4-to-16 Line Decoder/Demultiplexer with Input Latches

//適用於DE2-70 的程式

module Decoder4x16(

 input [17:0]SW,

 input [3:0] KEY,

 input  CLOCK_50,

 output [17:0] LEDR,

 output [7:0] LEDG,

 output [6:0] HEX0,

 output [6:0] HEX1,

 output [6:0] HEX2,

 output [6:0] HEX3,

 output [6:0] HEX4,

 output [6:0] HEX5,

 output [6:0] HEX6,

 output [6:0] HEX7

 );

assign HEX0=7'b111_1111;  //off 7-segment Display

assign HEX1=7'b111_1111;

assign HEX2=7'b111_1111;

assign HEX3=7'b111_1111;

assign HEX4=7'b111_1111;

assign HEX5=7'b111_1111;

assign HEX6=7'b111_1111;

assign HEX7=7'b111_1111;

// assign LEDR[17:0]=SW[17:0];  //SW status =>LEDR

wire [3:0]Q_out,Y,Y0,Y1,Y2,Y3;

wire clk_1hz;

//clk_div_1hz(clk_in , Reset, clk_out);

clk_div_1hz u1(CLOCK_50, KEY[0], clk_1hz);

divide_by_16 u2 (clk_1hz,KEY[0],Q_out);

/*

decoder2_4 u1({SW[3],SW[2]},SW[17],Y);

decoder2_4 u2({SW[1],SW[0]},Y[0],Y0);

decoder2_4 u3({SW[1],SW[0]},Y[1],Y1);

decoder2_4 u4({SW[1],SW[0]},Y[2],Y2);

decoder2_4 u5({SW[1],SW[0]},Y[3],Y3);

*/

decoder2_4 u3(Q_out[3:2],SW[17],Y);

decoder2_4 u4(Q_out[1:0],Y[0],Y0);

decoder2_4 u5(Q_out[1:0],Y[1],Y1);

decoder2_4 u6(Q_out[1:0],Y[2],Y2);

decoder2_4 u7(Q_out[1:0],Y[3],Y3);

assign LEDR[3:0]=Y0;

assign LEDR[7:4]=Y1;

assign LEDR[11:8]=Y2;

assign LEDR[15:12]=Y3;

endmodule

// File : 2 to 4 decoder using case statement.v

module decoder2_4 ( din ,ena ,dout );

input ena;

wire ena;

input [1:0] din ;

wire [1:0] din ;

output [3:0] dout ;

reg [3:0] dout ;

always @ (din or ena) begin

if (!ena) 

  dout=0;

 else begin 

 case (din)

  0 : dout = 1;

  1 : dout = 2;

  2 : dout = 4;

  default : dout = 8;

 endcase

 end

end

endmodule

module clk_div_1hz(clk_in , Reset, clk_out);

input clk_in ;

input Reset;

output reg  clk_out;

integer i;

always@(posedge clk_in or negedge Reset) begin

 if (!Reset) begin

   i=0;

   clk_out=0;

   end

 else begin

    i= i+1 ;

    if (i>=24_999_999) begin

        clk_out  = ~clk_out;

        i=0;

       end

    end    

end            

endmodule

module divide_by_16(clk_in , Reset,Q_out);

input clk_in ;

input Reset;

output reg[3:0] Q_out;

always@(posedge clk_in or negedge Reset) begin

 if (!Reset) 

   Q_out<=4'b0000;

   

 else  

  Q_out<= Q_out+1;

  

end            

endmodule