2014年6月16日 星期一

Verilog Code For IC74LS165 8-Bit Parallel In/Serial Output Shift Registers---適用於DE2-70



         74L165是並行輸入,串行輸出移位寄存器。80C51單片機內部的串列口在方式0工作狀態
 下,使用移位寄存器晶片可以擴展一個或多個8位並行I/O口。其引腳如圖所示。
  
 A, B, C, D, E, F, G, H 並行輸入端。
 QH串行輸出端。
 CLOCK:時鐘輸入端。
 CLOCK INHIBIT:時鐘禁止端。當時鐘禁止端CLK2為低電平時,充許時鐘輸入。
 SHIFT/LOAD:移位與置位控制端。
 SER:擴展多個74LS165的首尾連接端。

// 8-bit register can be cleared, loaded, shifted left
// Retains value if no control signal is asserted
module shiftReg (CLK, clr, shift, ld, Din, SI,Q7,Q7bar );
input CLK;
input clr; // clear register 
input shift; // shift
input ld; // load register from Din
input [7:0] Din; // Data input for load
input SI; // Input bit to shift in
output Q7,Q7bar;
//output [7:0] Dout;
reg [7:0] Dout;
always @(negedge CLK) 
begin
 if (!clr) Dout <= 0;
 else if (ld) Dout <= Din;
 else if (shift) Dout <= { Dout[6:0], SI };
 end

assign Q7=Dout[7];

assign Q7bar=~Q7;


endmodule // shiftReg


//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
module PISO_8bits_ShiftReg(
  input CLOCK_50,     //    50 MHz clock
  input [3:0] KEY,      //    Pushbutton[3:0]
  input [17:0] SW,     //    Toggle Switch[17:0]
  output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,  // Seven Segment Digits
  output [8:0] LEDG,   //    LED Green
  output [17:0] LEDR,   //    LED Red
  inout [35:0] GPIO_0,GPIO_1,    //    GPIO Connections
//    LCD Module 16X2
  output LCD_ON,     // LCD Power ON/OFF
  output LCD_BLON,     // LCD Back Light ON/OFF
  output LCD_RW,     // LCD Read/Write Select, 0 = Write, 1 = Read
  output LCD_EN,     // LCD Enable
  output LCD_RS,     // LCD Command/Data Select, 0 = Command, 1 = Data
  inout [7:0] LCD_DATA, // LCD Data bus 8 bits
  input  UART_RXD, //RS232 RXD
  output UART_TXD //RS232 TXD
);

//    All inout port turn to tri-state
assign    GPIO_0        =    36'hzzzzzzzzz;
assign    GPIO_1        =    36'hzzzzzzzzz;

assign HEX0=7'b111_1111;  //off 7-segment Display
assign HEX1=7'b111_1111;
assign HEX2=7'b111_1111;
assign HEX3=7'b111_1111;
assign HEX4=7'b111_1111;
assign HEX5=7'b111_1111;
assign HEX6=7'b111_1111;
assign HEX7=7'b111_1111;

//shiftReg (CLK, clr, shift, ld, Din, SI, Dout,Q7,Q7bar );

shiftReg (KEY[0],KEY[1],SW[15],SW[17],SW[7:0], SW[16],LEDR[7:0],LEDG[1],LEDG[0]);


endmodule


// 8-bit register can be cleared, loaded, shifted left
// Retains value if no control signal is asserted
module shiftReg (CLK, clr, shift, ld, Din, SI,Dout , Q7,Q7bar );
input CLK;
input clr; // clear register 
input shift; // shift
input ld; // load register from Din
input [7:0] Din; // Data input for load
input SI; // Input bit to shift in
output Q7,Q7bar;
output [7:0] Dout;
reg [7:0] Dout;
always @(negedge CLK) 
begin
 if (!clr) Dout <= 0;
 else if (ld) Dout <= Din;
 else if (shift) Dout <= { Dout[6:0], SI };
 end

assign Q7=Dout[7];

assign Q7bar=~Q7;


endmodule // shiftReg





//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

module PISO_8bits_ShiftReg(
  input CLOCK_50,     //    50 MHz clock
  input [3:0] KEY,      //    Pushbutton[3:0]
  input [17:0] SW,     //    Toggle Switch[17:0]
  output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,  // Seven Segment Digits
  output [8:0] LEDG,   //    LED Green
  output [17:0] LEDR,   //    LED Red
  inout [35:0] GPIO_0,GPIO_1,    //    GPIO Connections
//    LCD Module 16X2
  output LCD_ON,     // LCD Power ON/OFF
  output LCD_BLON,     // LCD Back Light ON/OFF
  output LCD_RW,     // LCD Read/Write Select, 0 = Write, 1 = Read
  output LCD_EN,     // LCD Enable
  output LCD_RS,     // LCD Command/Data Select, 0 = Command, 1 = Data
  inout [7:0] LCD_DATA, // LCD Data bus 8 bits
  input  UART_RXD, //RS232 RXD
  output UART_TXD //RS232 TXD
);

//    All inout port turn to tri-state
assign    GPIO_0        =    36'hzzzzzzzzz;
assign    GPIO_1        =    36'hzzzzzzzzz;

assign HEX0=7'b111_1111;  //off 7-segment Display
assign HEX1=7'b111_1111;
assign HEX2=7'b111_1111;
assign HEX3=7'b111_1111;
assign HEX4=7'b111_1111;
assign HEX5=7'b111_1111;
assign HEX6=7'b111_1111;
assign HEX7=7'b111_1111;

//shiftReg (CLK, clr, shift, ld, Din, SI, Dout,Q7,Q7bar );

shiftReg (KEY[0],KEY[1],SW[15],SW[17],SW[7:0], SW[16],LEDG[1],LEDG[0]);


endmodule


// 8-bit register can be cleared, loaded, shifted left
// Retains value if no control signal is asserted
module shiftReg (CLK, clr, shift, ld, Din, SI,Q7,Q7bar );
input CLK;
input clr; // clear register 
input shift; // shift
input ld; // load register from Din
input [7:0] Din; // Data input for load
input SI; // Input bit to shift in
output Q7,Q7bar;
//output [7:0] Dout;
reg [7:0] Dout;
always @(negedge CLK) 
begin
 if (!clr) Dout <= 0;
 else if (ld) Dout <= Din;
 else if (shift) Dout <= { Dout[6:0], SI };
 end

assign Q7=Dout[7];

assign Q7bar=~Q7;


endmodule // shiftReg
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

沒有留言:

張貼留言