Verilog HDL Operands
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1. Literals
string (bit & character)
Numeric
real
Character string literals:
These are sequences of characters and are useful when designing simulatable test harnesses around a synthesizable model. For example, "ABC".
Numeric Literals:
Numeric literals are simple constant numbers that may be specified in binary, octal, decimal or hexadecimal. The specification of its size is optional as Verilog calsulates size based on the longest operand value in an expression, and corresponding assigned value in an assignment. Examples are shown below.
12'b0011_0101_1100 12-bit sized binary constant number
2'O57 2 digit octal number
3_14159 default decimal number
4'h9FDE 4 digit hexadecimal number
module Literals (A1, A2, B1, B2, Y1, Y2);
input A1, A2, B1, B2;
output [7:0] Y1;
output [5:0] Y2;
parameter CST=4'b1010;
parameter twentyfive=25; //numeric literal
reg [7:0] Y1;
reg [5:0] Y2;
always @(A or A2 or B1 or B2 or Y1 or Y2)
begin
//parenthesis are needed to be syntatically correct
if (A1==1)
Y1={CST,4'b0101}; //bit string literal
else if (A2==1)
Y1={CST,4'b0111}; //bit string literal
else
Y1={CST,4'b1111}; //bit string literal
if (B==0)
Y2=10; //integer literal
else if (B2==1)
Y2=15; //integer literal
else
Y2=twentyfive+10+15; //integer literal end
endmodule
2. Identifiers
Module
Parameter
Wire
Register
macros (text substitutions)
An identifier is used to give a name to a data object so that it may be easily referenced in a model. They are the most commonly used type of operand. The value of the named object is returned as the operand value. Verilog is case sensitive, so upper and lower case identifier names are treated as being different identifiers.
module Identifier (A, B, C, D, E, Y1, Y2);
input A, B, C, D; //identifiers
input [7:0] E;
output Y1, Y2;
reg F, Y1, Y2; //identifiers
function AND_OR_Bits;
input [7:0] A;
begin
AND_OR_Bits=(A[7] & A[6] & A[5] & A[4]) & (A[3] | A[2] | A[1] | A[0]);
end
endfunction
always @(A or B or C or D or E)
begin
F=A&B&AND_OR_Bits(E);
Y1=C&F;
Y2=D|F;
end
endmodule
3. Function calls
Function calls, which must reside in an expression, are operands. The single value returned from a function is the operand value used in the expression.
module Functional_Calls (A1, A2, A3, A4, B1, B2, Y1, Y2);
input A1, A2, A3, A4, B1, B2;
output Y1, Y2;
reg Y1, Y2;
function function1;
input F1, F2, F3, F4;
begin
function1=(F1 & F2) | (F3 & F4);
end
endfunction
always @(A1 or A2 or A3 or A4 or B1 or B2)
begin
Y1=function1(A1,A2,A3,A4)|B1|B2;
Y2=B1||B2||function1(A1,A2,A3,A4);
end
endmodule
4. Index and Slice Name
An index named operand specifies a single element of an array. For synthesis the array may be of type constant, variable, or signal. A slice named operand is a sequence of elements within an arraty and is identified Verilog using the colon ":".
module Index_Slice_Name (A, B, Y);
input [5:0] A, B;
output [11:0] Y;
parameter C=3'b100; reg [11:0] Y;
always @(A or B)
begin
Y[2:0]=A[0:2]; //swap bits
Y[3]=A[3]&B[3]; //single index
Y[5:4]={A[5]&B[5],A[4]|B[4]};
Y[8:6]=B[2:0]; //3-bit slice
Y[11:9]=C;
end
endmodule
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