TRAFFIC light CONTROLLER ---適用於DE2-70 的程式

module traffic_light(  //適用於DE2-70 的程式
 input [17:0]SW,
 input [3:0] KEY,
 input  CLOCK_50,

 output [17:0] LEDR,
 output [7:0] LEDG,
 output [6:0] HEX0,
 output [6:0] HEX1,
 output [6:0] HEX2,
 output [6:0] HEX3,
 output [6:0] HEX4,
 output [6:0] HEX5,
 output [6:0] HEX6,
 output [6:0] HEX7
 );

assign HEX0=7'b111_1111;  //off 7-segment Display
assign HEX1=7'b111_1111;
assign HEX2=7'b111_1111;
assign HEX3=7'b111_1111;
assign HEX4=7'b111_1111;
assign HEX5=7'b111_1111;
assign HEX6=7'b111_1111;
assign HEX7=7'b111_1111;

wire clk_1hz;
wire [5:0]RGB;
assign LEDG[0]=clk_1hz;
assign LEDR[17:15]=RGB[5:3];
assign LEDR[2:0]=RGB[2:0];



clk_div_1hz u1(CLOCK_50, KEY[0], clk_1hz);
Main_traffic_light u2(clk_1hz,KEY[0],RGB);

endmodule


 
module Main_traffic_light(clk, clr, lights);
    input clk;
    input clr;
    output reg [5:0] lights;
reg [2:0] state;
reg [2:0] count;
reg [1:0] q;
 
parameter s0=3'b000, s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100,s5=3'b101;
parameter sec5= 3'b101,sec1=3'b001;
 
always @ (posedge clk or negedge clr)
begin
if (!clr==1)
q<=0;
else
q<=q+1;
end
 
always @ (posedge q[1] or negedge clr)
begin
if (!clr==1)
begin
state<=s0;
count<=0;
end 
else
case (state)
s0: if (count<sec5)
begin 
state <=s0;
count<=count+1;
end
else
begin
state<=s1;
count<=0;
end
s1: if (count<sec1)
begin 
state <=s1;
count<=count+1;
end
else
begin
state<=s2;
count<=0;
end
s2: if (count<sec1)
begin 
state <=s2;
count<=count+1;
end
else
begin
state<=s3;
count<=0;
end
s3: if (count<sec5)
begin 
state <=s3;
count<=count+1;
end
else
begin
state<=s4;
count<=0;
end
s4: if (count<sec1)
begin 
state <=s4;
count<=count+1;
end
else
begin
state<=s5;
count<=0;
end
s5: if (count<sec1)
begin 
state <=s5;
count<=count+1;
end
 else
begin
state<=s0;
count<=0;
end

default:state<=s0;
endcase
end
 
 
always @ (*)
begin
case (state)
s0:lights= 6'b100001;
s1:lights= 6'b100010;
s2:lights= 6'b100100;
s3:lights= 6'b001100;
s4:lights= 6'b010100;
s5:lights= 6'b100100;
default:lights= 6'b100001;
endcase
end
 
endmodule

module clk_div_1hz(clk_in , Reset, clk_out);
input clk_in ;
input Reset;
output reg  clk_out;

integer i;
always@(posedge clk_in or negedge Reset) begin
 if (!Reset) begin
   i=0;
   clk_out=0;
   end
 else begin
    i= i+1 ;
    if (i>=24_999_999) begin
        clk_out  = ~clk_out;
        i=0;
       end
    end    
end            

endmodule