使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計SR Latch (gated)為例(Test Bench開發平台)

使用Quartus-II 9.1SP2 + ModelSim 6.5b-Aletra + Altera DE2-115 FPGA開發平台，設計SR Latch (gated)為例(Test Bench開發平台)

//sr_latch_gated

module sr_latch_gated(Q, Qn, G, S, R);
   output Q;
   output Qn;
   input  G;   
   input  S;
   input  R;
   wire   S1;
   wire   R1;
   
   and(S1, G, S);
   and(R1, G, R);   
   nor(Qn, S1, Q);
   nor(Q, R1, Qn);
endmodule

`timescale 1us/10ps

module tb_sr_latch_gated;

reg tS;

reg tR;

reg tG;

wire tQ, tQn;

//module sr_latch_gated(Q, Qn, G, S, R);

sr_latch_gated  DUT(tQ, tQn, tG, tS, tR);

//instantiate counter to be tested.

initial

begin

    #5  tG=0;

#10 tS=1'b1;tR=1'b0;

#20 tS=1'b0;tR=1'b1;

#30 tS=1'b1;tR=1'b0;

#40 tS=1'b0;tR=1'b0;

#45  tG=1;

#50 tS=1'b1;tR=1'b0;

#60 tS=1'b0;tR=1'b1;

#70 tS=1'b1;tR=1'b1;

#80 tS=1'b0;tR=1'b1;

#100 $stop;

end

endmodule