HBLbits_Verilog Basic_Always casez

 HBLbits_Verilog Basic_Always casez

casez is for: It treats bits that have the value z as don't-care in the comparison.

For example, this would implement the 4-input priority encoder from the previous exercise:

always @(*) begin
    casez (in[3:0])
        4'bzzz1: out = 0;   // in[3:1] can be anything
        4'bzz1z: out = 1;
        4'bz1zz: out = 2;
        4'b1zzz: out = 3;
        default: out = 0;
    endcase
end

Build a priority encoder for 8-bit inputs.

/ synthesis verilog_input_version verilog_2001
module top_module (
    input [7:0] in,
    output reg [2:0] pos  );
 
always @(*) begin
    casez (in[7:0])
        8'bzzzz_zzz1: pos = 3'b000;   // in[7:1] can be anything
        8'bzzzz_zz1z: pos = 3'b001;
        8'bzzzz_z1zz: pos = 3'b010;
        8'bzzzz_1zzz: pos = 3'b011;
        
        8'bzzz1_zzzz: pos = 3'b100;   
        8'bzz1z_zzzz: pos = 3'b101;
        8'bz1zz_zzzz: pos = 3'b110;
        8'b1zzz_zzzz: pos = 3'b111;        
        default: pos = 0;
    endcase
end  
endmodule