HBLbits_Verilog Basic_Shift4

HBLbits_Verilog Basic_Shift4 

Build a 4-bit shift register (right shift), with asynchronous reset, synchronous load, and enable.

• areset: Resets shift register to zero.
• load: Loads shift register with data[3:0] instead of shifting.
• ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears).
• q: The contents of the shift register.

If both the load and ena inputs are asserted (1), the load input has higher priority.

//正確寫法

module top_module(
    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    always@ (posedge clk, posedge areset) begin //正確寫法
        if (areset) 
            q<=4'b0000;
        else if (load)
            q<=data;
        else if (ena)
            q<=q>>1;
        else
            q<=q;
            
    end
endmodule

//錯誤的寫法

module top_module(

    input clk,
    input areset,  // async active-high reset to zero
    input load,
    input ena,
    input [3:0] data,
    output reg [3:0] q); 
    always@ (posedge clk) begin  //錯誤的寫法
        if (areset) 
            q<=4'b0000;
        else if (load)
            q<=data;
        else if (ena)
            q<=q>>1;
        else
            q<=q;
            
    end
endmodule