HBLbits_Verilog Basic_Exams/ece241 2014 q4
Given the finite state machine circuit as shown, assume that the D flip-flops are initially reset to zero before the machine begins.
Build this circuit.
module top_module (
input clk,
input x,
output z
);
reg q,q1,q2;
always @(posedge clk)
begin
q<= q^x;
q1<= ~q1 && x;
q2<= ~q2 || x;
end
assign z=~(q | q1 | q2);
endmodule
input clk,
input x,
output z
);
reg q,q1,q2;
always @(posedge clk)
begin
q<= q^x;
q1<= ~q1 && x;
q2<= ~q2 || x;
end
assign z=~(q | q1 | q2);
endmodule
//另一方法
module top_module (
input clk,
input x,
output z
);
wire d1,d2,d3;
reg q1=0,q2=0,q3=0;
assign d1 = q1^x;
assign d2 = x&~q2;
assign d3 = x|~q3;
dff dff1 (d1,clk,q1);
dff dff2 (d2,clk,q2);
dff dff3 (d3,clk,q3);
assign z = ~(q1|q2|q3);
endmodule
module dff (input d,
input clk,
output reg q);
always@(posedge clk) begin
q <= d;
end
endmodule
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