HBLbits_Verilog Basic_Mt2015 lfsr

HBLbits_Verilog Basic_Mt2015 lfsr 

Taken from 2015 midterm question 5. See also the first part of this question: mt2015_muxdff

Write the Verilog code for this sequential circuit (Submodules are ok, but the top-level must be named top_module). Assume that you are going to implement the circuit on the DE1-SoC board. Connect the R inputs to the SW switches, connect Clock to KEY[0], and L to KEY[1]. Connect the Q outputs to the red lights LEDR.

module top_module (
input [2:0] SW,      // R
input [1:0] KEY,     // L and clk
output reg [2:0] LEDR);  // Q

    wire clk = KEY[0];
    wire L = KEY[1];
    wire [2:0] d = (L)?SW:{LEDR[1]^LEDR[2],LEDR[0],LEDR[2]};
    
    always @(posedge clk)begin
            LEDR <= d;
    end
endmodule

module top_module (

    input clk,
    input w, R, E, L,
    output Q
);
    wire [1:0] con = {E,L};
    always @(posedge clk) begin
        case(con) 
            2'b00: Q <= Q;
            2'b01: Q <= R;
            2'b11: Q <= R;
            2'b10: Q <= w;
        endcase
        
    end
    
endmodule