HBLbits_Verilog Basic_Always case

 HBLbits_Verilog Basic_Always case 

Case statements in Verilog are nearly equivalent to a sequence of if-elseif-else that compares one expression to a list of others.

always @(*) begin     // This is a combinational circuit
    case (in)
      1'b1: begin 
               out = 1'b1;  // begin-end if >1 statement
            end
      1'b0: out = 1'b0;
      default: out = 1'bx;
    endcase
end

create a 6-to-1 multiplexer. When sel is between 0 and 5, choose the corresponding data input. Otherwise, output 0. The data inputs and outputs are all 4 bits wide.

// synthesis verilog_input_version verilog_2001
module top_module ( 

     input [2:0] sel, 

     input [3:0] data0, 

     input [3:0] data1, 

     input [3:0] data2, 

     input [3:0] data3, 

     input [3:0] data4, 

     input [3:0] data5, 

     output reg [3:0] out   );

    always@(*) begin  // This is a combinational circuit 

     case(sel) 

         3'd0: out=data0; 

         3'd1: out=data1; 

         3'd2: out=data2; 

         3'd3: out=data3; 

         3'd4: out=data4; 

         3'd5: out=data5; 

         default: out=4'd0; 

     endcase 

     end 

 endmodule