HBLbits_Verilog Basic_Countslow
Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the slowena input indicates when the counter should increment.
Near first mismatch at time 310
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q);
always @(posedge clk) begin
if (reset || q==4'd9)
q = 4'd0;
else if (slowena)
q = q + 1;
else
q=q;
end
endmodule
input clk,
input slowena,
input reset,
output [3:0] q);
always @(posedge clk) begin
if (reset || q==4'd9)
q = 4'd0;
else if (slowena)
q = q + 1;
else
q=q;
end
endmodule
//修改成
module top_module (
input clk,
input slowena,
input reset,
output [3:0] q);
always@(posedge clk)
begin
if(reset) q<=4'b0000;
else if(slowena == 1 & q<4'b1001)
q<=q+1'b1;
//这里一定要与上q<4'b1001,不然在使能状态下会一直累加
else if (q==4'b1001 & slowena == 1)
q<=4'b0000;
//这里与上slowena， 使得计数器数到9时也能够保持
else
q<=q;
end
endmodule
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