HBLbits_Verilog Basic_Mt2015 q4a

HBLbits_Verilog Basic_Mt2015 q4a 

Module A is supposed to implement the function z = (x^y) & x. Implement this module.

module top_module (input x, input y, output z);
    module_A(x,y,z);
endmodule

module module_A (input x, input y, output z);
    assign z = (x^y)& x ;
endmodule