HBLbits_Verilog Basic_Exams/ece241 2014 q3

 HBLbits_Verilog Basic_Exams/ece241 2014 q3

For the following Karnaugh map, give the circuit implementation using one 4-to-1 multiplexer and as many 2-to-1 multiplexers as required, but using as few as possible. You are not allowed to use any other logic gate and you must use a and b as the multiplexer selector inputs, as shown on the 4-to-1 multiplexer below.

module top_module (
    input c,
    input d,
    output [3:0] mux_in
); 
    always@(*) begin
        case({c,d})
            2'b00: mux_in=4'b0100;
            2'b01: mux_in=4'b0001;
            2'b11: mux_in=4'b1001;
            2'b10: mux_in=4'b0101;
        endcase    
    end
  //  assign mux_in = (c&d)?4'b1001:(c)?4'b0101:(d)?4'b0001:4'b0100;
 
endmodule