HBLbits_Verilog Basic_Mt2015 q4

HBLbits_Verilog Basic_Mt2015 q4

 See mt2015_q4a and mt2015_q4b for the submodules used here. The top-level design consists of two instantiations each of subcircuits A and B, as shown below.

IA1 & 1A2 ==>function z = (x^y) & x.

IB1 & 1B2 ==>function z = ~(x^y);

module top_module (input x, input y, output z);
    wire w0,w1,w2,w3;
    A u0(x,y,w0);
    B u1(x,y,w1);
    A u2(x,y,w2);
    B u3(x,y,w3);
    assign z= (w0|w1) ^ (w2&w3);
endmodule

module A (input x , input y ,output z);
    assign z = (x^y) & (x) ;
endmodule

module B (input x , input y ,output z);
    assign z = ((~x)&(~y)) | (x&y);
endmodule