Verilog HDL刷题笔记（05）

 Verilog HDL刷题笔记（05）(Circuit-Combinational Logic-Multiplexers)

61.Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

module top_module( 
    input a, b, sel,
    output out ); 
    assign out=(sel)?b:a;
endmodule
//或者采用逻辑表达式
//    assign out = (sel & b) | (~sel & a);

62.Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

module top_module( 
    input a, b, sel,
    output out ); 
    assign out=(sel)?b:a;
endmodule
    // The following doesn't work. Why?
    // assign out = (sel & b) | (~sel & a);

63.Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
    always@(*) begin
        case(sel)
            4'b0000: out=a;
            4'b0001: out=b;
            4'b0010: out=c;
            4'b0011: out=d;
            4'b0100: out=e;
            4'b0101: out=f;
            4'b0110: out=g;
            4'b0111: out=h;
            4'b1000: out=i;
            default: out=16'b1111111111111111;
        endcase
    end
endmodule
//
//答案
//
always @(*) begin
        out = '1;        // '1 is a special literal syntax for a number with all bits set to 1.
                        // '0, 'x, and 'z are also valid.
                        // I prefer to assign a default value to 'out' instead of using a
                        // default case.
        case (sel)
            4'h0: out = a;
            4'h1: out = b;
            4'h2: out = c;
            4'h3: out = d;
            4'h4: out = e;
            4'h5: out = f;
            4'h6: out = g;
            4'h7: out = h;
            4'h8: out = i;
        endcase
    end
    
endmodule
//case的条件没有列举完全不是会有latch来着？？？

64.Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
    assign out=in[sel];
endmodule

65.Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.

HINT:

• With this many options, a case statement isn't so useful.
• Vector indices can be variable, as long as the synthesizer can figure out that the width of the bits being selected is constant. It's not always good at this. An error saying "... is not a constant" means it couldn't prove that the select width is constant. In particular, in[ sel*4+3 : sel*4 ] does not work.
• Bit slicing ("Indexed vector part select", since Verilog-2001) has an even more compact syntax.

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    assign out[3] = in[sel*4+3];
    assign out[2] = in[sel*4+2];
    assign out[1] = in[sel*4+1];
    assign out[0] = in[sel*4];
endmodule
//
//答案
//
assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};
    // We can't part-select multiple bits without an error, but we can select one bit at a time,
    // four times, then concatenate them together.
    //
    // Alternatively, "indexed vector part select" works better, but has an unfamiliar syntax:
    // assign out = in[sel*4 +: 4];        // Select starting at index "sel*4", then select a total width of 4 bits with increasing (+:) index number.
    // assign out = in[sel*4+3 -: 4];    // Select starting at index "sel*4+3", then select a total width of 4 bits with decreasing (-:) index number.
    // Note: The width (4 in this case) must be constant.

 

分类: Verilog HDL