HBLbits_Verilog Basic_Always nolatches

 HBLbits_Verilog Basic_Always nolatches

PS/2 keyboard for a game. Given the last two bytes of scancodes received,

Scancode [15:0]	Arrow key
16'he06b	left arrow
16'he072	down arrow
16'he074	right arrow
16'he075	up arrow
Anything else	none

One easy way around this is to assign a "default value" to the outputs before the case statement:

always @(*) begin
    up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
    case (scancode)
        ... // Set to 1 as necessary.
    endcase
end

This style of code ensures the outputs are assigned a value (of 0) in all possible cases unless the case statement overrides the assignment. This also means that a default: case item becomes unnecessary.

// synthesis verilog_input_version verilog_2001

module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
    
always @(*) begin
    up = 1'b0; down = 1'b0; left = 1'b0; right = 1'b0;
    case (scancode)
        16'he06b: left= 1'b1;
        16'he072: down= 1'b1;
        16'he074: right= 1'b1;
        16'he075: up= 1'b1;
    endcase
end
endmodule