HBLbits_Verilog Basic_module_shift
The module provided to you is: module my_dff ( input clk, input d, output q );
module top_module ( input clk, input d, output q );
wire a, b; // Create two wires.
my_dff inst1 ( clk, d, a );
my_dff inst2 ( clk, a, b );
my_dff inst3 ( clk, b, q );
endmodule
wire a, b; // Create two wires.
my_dff inst1 ( clk, d, a );
my_dff inst2 ( clk, a, b );
my_dff inst3 ( clk, b, q );
endmodule
沒有留言:
張貼留言