HBLbits_Verilog Basic_Exams/m2014 q4e
Implement the following circuit:
module top_module (
input in1,
input in2,
output out);
assign out = ~(in1 | in2);
endmodule
input in1,
input in2,
output out);
assign out = ~(in1 | in2);
endmodule
作業2 MQTT (Relay + DHT22) 控制 ------- 利用Node-Red 1) 安裝Node-Red https://ithelp.ithome.com.tw/articles/10201795 https://www.youtube.com/watch?v...
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