2021年4月24日 星期六

HBLbits_Verilog Basic_Exams/2012 q1g

HBLbits_Verilog Basic_Exams/2012 q1g 

Consider the function f shown in the Karnaugh map below. Implement this function.

(The original exam question asked for simplified SOP and POS forms of the function.)



  f= x2' x4' + x1' x3+ x2 x3 x4

module top_module (
    input [4:1] x,
    output f
); 
 // f= x2' x4' + x1' x3+ x2 x3 x4
    assign f = (~x[2] & ~x[4]) | (~x[1]&x[3]) | (x[2]&x[3]&x[4]) ;
endmodule

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