HBLbits_Verilog Basic_Step one , Zero , Wire

HBLbits_Verilog Basic_ One  , Zero , Wire

module top_module ( zero );
    output zero;
    // Verilog-1995
endmodule

module top_module ( output zero ); 

    // Verilog-2001
endmodule

Step one

module top_module(

     output one );
assign one = 1'b1;
endmodule

Zero

module top_module(
    output zero
);// Module body starts after semicolon
assign zero=1'b0;
endmodule

Wire

module top_module( input in, output out );

    wire w1;

assign w1=in;

    assign out=w1;

endmodule