HBLbits_Verilog Basic_Mt2015 muxdff

HBLbits_Verilog Basic_Mt2015 muxdff

Taken from ECE253 2015 midterm question 5

Consider the sequential circuit below:

Assume that you want to implement hierarchical Verilog code for this circuit, using three instantiations of a submodule that has a flip-flop and multiplexer in it. Write a Verilog module (containing one flip-flop and multiplexer) named top_module for this submodule.

module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q);
  wire d;
    always@(posedge clk)
        Q<=d;
    assign d=(L)?r_in:q_in;
 endmodule
//另一方法
module top_module (
input clk,
input L,
input r_in,
input q_in,
output reg Q);
    
    always @ (posedge clk) begin
        case (L)
            1'b0 : Q <= q_in;
            1'b1 : Q <= r_in;
        endcase    
    end
endmodule