HBLbits_Verilog Basic_Fadd
Create a full adder. A full adder adds three bits (including carry-in) and produces a sum and carry-out.
module top_module(
input a, b, cin,
output cout, sum );
assign {cout, sum}=a+b+cin;
//assign cout = a & b | a & cin | b & cin;
//assign sum = a ^ b ^ cin;
endmodule
input a, b, cin,
output cout, sum );
assign {cout, sum}=a+b+cin;
//assign cout = a & b | a & cin | b & cin;
//assign sum = a ^ b ^ cin;
endmodule
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