HBLbits_Verilog Basic_Mt2015 q4b

HBLbits_Verilog Basic_Mt2015 q4b

Circuit B can be described by the following simulation waveform: 

Implement this circuit.

module top_module (input x, 

                   input y, 
                   output z );
    assign z = ((~x)&(~y)) | (x&y);
endmodule

module top_module(

input x,

input y,

output z);

// The simulation waveforms gives you a truth table:

// y x   z

// 0 0   1

// 0 1   0

// 1 0   0

// 1 1   1   

// Two minterms: 

// assign z = (~x & ~y) | (x & y);

// Or: Notice this is an XNOR.

assign z = ~(x^y);

endmodule