HBLbits_Verilog Basic_Dualedge

 HBLbits_Verilog Basic_Dualedge

flip-flops that are triggered on the positive edge of the clock, or negative edge of the clock. A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list.

Build a circuit that functionally behaves like a dual-edge triggered flip-flop:

module top_module (

    input clk,

    input d,

    output q

);

reg p, n;

// A positive-edge triggered flip-flop

    always @(posedge clk)

        p <= d ^ n;

        

    // A negative-edge triggered flip-flop

    always @(negedge clk)

        n <= d ^ p;

    

    // Why does this work? 

    // After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.

    // After negedge clk, n changes to p^n. Thus q = (p^n) = (p^p^n) = d.

    // At each (positive or negative) clock edge, p and n FFs alternately

    // load a value that will cancel out the other and cause the new value of d to remain.

    assign q = p ^ n;

// Can't synthesize this.

/*always @(posedge clk, negedge clk) begin

q <= d;

end*/

endmodule