Verilog 硬體描述語言 HDL
Ch08 pili_2.v 七段顯示霹靂燈
//=================================================
//需 Import pin assignments DE2_115_pin_assignments
//=================================================
//Verilog 硬體描述語言 HDL
// Ch08 pili_2.v
// 七段顯示霹靂燈
//=================================================module Pili (
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR // LED Red
);
// blank unused 7-segment digits
//assign HEX0 = 7'b111_1111;
assign HEX1 = 7'b111_1111;
assign HEX2 = 7'b111_1111;
//assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;
assign LEDR=SW;
// Setup clock divider
wire [6:0] myclock;
/*
divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
*/
clock_divider cdiv(CLOCK_50,KEY[3],myclock);
//module clock_divider(CLK,RST,clock);
pili_module (myclock[0],KEY[0],HEX0);
//module pili_2 (Clk,Clr,Q,seg7);
pili_2 (myclock[0],KEY[0],LEDG[3:0],HEX3);
endmodule
//=================================================
module clock_divider(CLK,RST,clock);
input CLK,RST;
output [6:0] clock;
wire clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz;
assign clock = {clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz};
divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
endmodule
module divide_by_10(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [2:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 3'b000;
end
else if (count < 4)
begin
count <= count+1'b1;
end
else
begin
count <= 3'b000;
Q <= ~Q;
end
end
endmodule
module divide_by_50(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [4:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 5'b00000;
end
else if (count < 24)
begin
count <= count+1'b1;
end
else
begin
count <= 5'b00000;
Q <= ~Q;
end
end
endmodule
//=================================================
// Ch08 pili_1.v
// 七段顯示霹靂燈
module pili_module (Clk,Clr,seg7);
input Clk,Clr; // 一位元輸入
output [6:0]seg7; // 一位元輸出
reg [6:0]L=7'b0000001; // 宣告為暫存器資料
// 上緣觸發時脈, 上緣同步清除
always@ (posedge Clk)
if (~Clr) L = 7'b0000001; // A, 順時針
else if (L == 7'b0000001) L = 7'b0000010; // B, 順時針
else if (L == 7'b0000010) L = 7'b0000100; // C, 順時針
else if (L == 7'b0000100) L = 7'b0001000; // D, 順時針
else if (L == 7'b0001000) L = 7'b0010000; // E, 順時針
else if (L == 7'b0010000) L = 7'b0100000; // F, 順時針
else if (L == 7'b0100000) L = 7'b1000001; // A, 逆時針
else if (L == 7'b1000001) L = 7'b1100000; // F, 逆時針
else if (L == 7'b1100000) L = 7'b1010000; // E, 逆時針
else if (L == 7'b1010000) L = 7'b1001000; // D, 逆時針
else if (L == 7'b1001000) L = 7'b1000100; // C, 逆時針
else if (L == 7'b1000100) L = 7'b1000010; // B, 逆時針
else if (L == 7'b1000010) L = 7'b0000001; // A, 順時針
else L = 7'b0000000; // 不顯示
assign seg7 = ~L[5:0];
endmodule
//=================================================
//Verilog 硬體描述語言 HDL
// Ch08 pili_2.v
// 七段顯示霹靂燈
module pili_2 (Clk,Clr,Q,seg7);
input Clk,Clr; // 一位元輸入
output [3:0] Q; // 四位元輸出
output [6:0]seg7; // 一位元輸出
reg [3:0] Q; // 宣告為暫存器資料
reg [5:0] L; // 宣告為暫存器資料
// 上緣觸發時脈, 上緣同步清除, 模式12上數計數器
always@ (posedge Clk)
if (~Clr) Q = 1;
else if (Q == 12) Q = 1; // 計數值 1 ~ 12
else Q = Q + 1;
// 七段顯示, 組合邏輯電路
always@ (Q)
case (Q)
1 : L = 6'b000001; // A, 順時針
2 : L = 6'b000010; // B, 順時針
3 : L = 6'b000100; // C, 順時針
4 : L = 6'b001000; // D, 順時針
5 : L = 6'b010000; // E, 順時針
6 : L = 6'b100000; // F, 順時針
7 : L = 6'b000001; // A, 逆時針
8 : L = 6'b100000; // F, 逆時針
9 : L = 6'b010000; // E, 逆時針
10 : L = 6'b001000; // D, 逆時針
11 : L = 6'b000100; // C, 逆時針
12 : L = 6'b000010; // B, 逆時針
default : L = 6'b000000; // 不顯示
endcase
assign seg7 = ~L;
endmodule
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