13bit Binary to BCD code (DE2-115)

 13bit Binary to BCD code (max : 8191)

//=====================================================
// Verilog 硬體描述語言 HDL
// Ch08  13bit Binary to BCD code
//=====================================================
module Binary2BCD(
  input  CLOCK_50, // 50 MHz clock
  input  [3:0] KEY,      // Pushbutton[3:0]
  input  [17:0] SW, // Toggle Switch[17:0]
  output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,  // Seven Segment Digits
  output [8:0] LEDG,  // LED Green
  output [17:0] LEDR   // LED Red
 );
 // blank unused 7-segment digits
//assign HEX0 = 7'b111_1111;
//assign HEX1 = 7'b111_1111;
//assign HEX2 = 7'b111_1111;
//assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;

wire [7:0] segout0;   //HEX 0
wire [7:0] segout1;   //HEX 1
wire [7:0] segout2;   //HEX 2
wire [7:0] segout3;   //HEX 3
// Setup clock divider
wire [6:0] myclock;

/*
 divide_by_50 d6(clk_1Mhz,CLK,RST);
 divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
 divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
 divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
 divide_by_10 d2(clk_100hz,clk_1Khz,RST);
 divide_by_10 d1(clk_10hz,clk_100hz,RST);
 divide_by_10 d0(clk_1hz,clk_10hz,RST);
*/
 clock_divider clkdiv(CLOCK_50,KEY[3],myclock);

 //module clock_divider(CLK,RST,clock);

 //smg4( clk,rst_n,number,            //input
 //      ones,tens,hundreds,thousand  //output);
//input clk;
//input rst_n;
//input [12:0] number;
//output [6:0] ones,tens,hundreds,thousand;       
  assign LEDR=SW;
  wire[3:0] ones, tens ,hundreds ,thousands ;
  assign LEDG[7]=myclock[1];
  smg4(CLOCK_50,KEY[3],SW[12:0],HEX3,HEX2,HEX1,HEX0);


endmodule

//=====================================================
//??管?示四位?字  max=8191
module smg4(
        clk,rst_n,number,      //input
        qian,bai,shi,ge       //output
);
input clk;
input rst_n;
input [12:0] number;
output [6:0] qian,bai,shi,ge;

reg [3:0] q,b,s,g;

// 加三移位法 13位的二?制 只需要16位?存其十?制?字 一共29位 28:0
reg [3:0] count;
reg [28:0] temp;
//---------------- ??部分 -----------------
always@(posedge clk or negedge rst_n )
begin
 if(!rst_n ) 
   count<=0;
 else if(count==14)
   begin
    count<=0;
    q<=temp[28:25];
    b<=temp[24:21];
    s<=temp[20:17];
    g<=temp[16:13];
   end
 else
   count<=count+1;
end
//------------------加三移位法---------------
always@(posedge clk,negedge rst_n)
begin
    if(!rst_n) temp=0;
    else if(count==4'b0) temp={16'b0, number};
    else if(count<=13)
        begin
           if(temp[24:21]>4) temp[24:21]=temp[24:21]+3;
           if(temp[20:17]>4) temp[20:17]=temp[20:17]+3;
           if(temp[16:13]>4) temp[16:13]=temp[16:13]+3;
           temp=temp<<1;
        end
end
//------------------七段??--------------------
assign qian=qiduan(q);
assign bai=qiduan(b);
assign shi=qiduan(s);
assign ge=qiduan(g);


function [6:0] qiduan;
input [3:0] s;
qiduan=(s==0)?7'b1000000:
       (s==1)?7'b1111001:
       (s==2)?7'b0100100:
   (s==3)?7'b0110000:
   (s==4)?7'b0011001:
   (s==5)?7'b0010010:
   (s==6)?7'b0000010:
   (s==7)?7'b1111000:
   (s==8)?7'b0000000:
   7'b0010000;
endfunction


endmodule 

//=====================================================

module clock_divider(CLK,RST,clock);

 input CLK,RST;

 output [6:0] clock;

 wire clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz;

 assign clock = {clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz};

 divide_by_50 d6(clk_1Mhz,CLK,RST);

 divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);

 divide_by_10 d4(clk_10Khz,clk_100Khz,RST);

 divide_by_10 d3(clk_1Khz,clk_10Khz,RST);

 divide_by_10 d2(clk_100hz,clk_1Khz,RST);

 divide_by_10 d1(clk_10hz,clk_100hz,RST);

 divide_by_10 d0(clk_1hz,clk_10hz,RST);

endmodule

module divide_by_10(Q,CLK,RST);

input CLK, RST;

output Q;

reg Q;

reg [2:0] count;

always @ (posedge CLK or negedge RST)

 begin

  if (~RST)

   begin

    Q <= 1'b0;

    count <= 3'b000;

   end

  else if (count < 4)

   begin 

     count <= count+1'b1;

   end

  else 

   begin

    count <= 3'b000;

    Q <= ~Q;

   end

 end

endmodule

module divide_by_50(Q,CLK,RST);

input CLK, RST;

output Q;

reg Q;

reg [4:0] count;

always @ (posedge CLK or negedge RST)

 begin

  if (~RST)

   begin

    Q <= 1'b0;

    count <= 5'b00000;

   end

  else if (count < 24)

   begin 

     count <= count+1'b1;

   end

  else 

   begin

    count <= 5'b00000;

    Q <= ~Q;

   end

 end

endmodule