數位IC設計入門-Verilog Sequential logic Parallel in Parallel Out Shift register Behavioral Modeling (& Test Bench)

數位IC設計入門-Verilog Sequential logic 

 Parallel in Parallel Out Shift register Behavioral Modeling (& Test Bench)

//數位IC設計入門-Verilog Sequential logic 

// Parallel in Parallel Out Shift register Behavioral Modeling (& Test Bench)
//=======================================================

//File Name：PIPO_Shift_Register.v
module PIPO_Shift_Register(clock, clear, load, in, out);
input clock, clear, load;
input [3:0] in;
output [3:0] out;
reg [3:0] out;

always @(posedge clock)
begin
      if (clear)
      begin
            out = 4'd0;
      end

      else if (load)
      begin
            out = in;
      end

      else
      begin
            out[3] = out [2];
            out[2] = out [1];
            out[1] = out [0];
            out[0] = 1'd0;
      end
end

endmodule

//=======================================================
// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps    
module Test_bench;
 //PIPO_Shift_Register(clock, clear, load, in, out);
 //input clock, clear, load;
 //input [3:0] in;
 //output [3:0] out;

// Inputs
reg clock=0, clear=1, load=0;
reg [3:0]in=4'b1110;

// Outputs
wire [3:0]out;


// Instantiate the Unit Under Test (UUT)
// PIPO_Shift_Register(clock, clear, load, in, out);

PIPO_Shift_Register UUT (clock, clear, load, in, out);

initial begin
  $monitor(clock, clear, load, in, out);
  // Initialize Inputs
  #5  clear=0; load=1;
  #5  load=0;
  #20 clear=0;
  #10 load=1; in=4'b1110;
  #5  load=0;
  #20 load=1;in=4'b0101;
  #5  load=0;
  #30 load=1;in=4'b0101;
  #5  load=0;
  
  end

always #6 clock= ~clock;  

initial
begin
  #120;   // 模擬終止時間  120 ns
  $stop;
end


endmodule