數位IC設計入門-Verilog combinational logic ALU 算數邏輯單元 Behavioral Modeling (& Test Bench)

數位IC設計入門-Verilog combinational logic 
ALU 算數邏輯單元 Behavioral Modeling (& Test Bench) 

顯示得結果 用decimal 或unsigned Mode 

//數位IC設計入門-Verilog combinational logic 
//ALU 算數邏輯單元 Behavioral Modeling (& Test Bench) 
//Select = 0  ,  out = a+b   ;   Select = 1 , out =  a-b ;
//Select = 2  ,  out = a+1   ;   Select = 3 , out =  a-1 ;
//Select = 4  ,  out = a&b   ;   Select = 5 , out =  a | b ;
//Select = 6  ,  out = !b    ;   Select = 7 , out =  a^ b ;
//Select = 8  ,  out = a<<b  ;   Select = 9 , out =  a>>b ;
//Select =10..15 out=8'd0

  module ALU_8bit(select, a, b, out);
  input [3:0] select;
  input [7:0] a, b;
  output [7:0] out;
  reg [7:0] out;
  always@(select or a or b)
  begin
      case(select)
      4'b0000: out = a + b; //ADDITION
      4'b0001: out = a - b; //SUBTRACTION
      4'b0010: out = a + 1; //INCREMENT
      4'b0011: out = a - 1; //DECREMENT
      4'b0100: out = a & b; //AND
      4'b0101: out = a | b; //OR
      4'b0110: out = ! b; //NOT
      4'b0111: out = a ^ b; //XOR
      4'b1000: out = a << b; //SHIFT LEFT
      4'b1001: out = a >> b; // SHIFT RIGHT
      default: out = 8'b0; 
      endcase
  end
  endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps    
module Test_bench;
  //module ALU_8bit(select, a, b, out);
  //input [3:0] select;
  //input [7:0] a, b;
  //output [7:0] out;

// Inputs
reg [3:0]select=4'd0;
reg [7:0]a=8'd0 ;
reg [7:0]b=8'd0;

// Outputs
wire [7:0]out;


// Instantiate the Unit Under Test (UUT)
// ALU_8bit(select, a, b, out);

ALU_8bit UUT(select, a, b, out);

initial begin
 $monitor(select, a, b, out);

    // Initialize Inputs
 //#20 select[3:0]=4'd0 ; a=8'd0 ; b=8'd0;
 #20 select=4'd0 ; a=8'd4 ; b=8'd5;
 #20 select=4'd1 ; a=8'd4 ; b=8'd5;
 #20 select=4'd2 ; a=8'd4 ; b=8'd5;
 #20 select=4'd3 ; a=8'd4 ; b=8'd5;
 #20 select=4'd4 ; a=8'd4 ; b=8'd5;

 #20 select=4'd5 ; a=8'd4 ; b=8'd5;
 #20 select=4'd6 ; a=8'd4 ; b=8'd5;
 #20 select=4'd7 ; a=8'd4 ; b=8'd5;
 #20 select=4'd8 ; a=8'd4 ; b=8'd5;
 #20 select=4'd9 ; a=8'd4 ; b=8'd5;

 #20 select=4'd10 ; a=8'd4 ; b=8'd5;

 #20 select=4'd12 ; a=8'd4 ; b=8'd5;



end

initial
begin
  #250;   // 模擬終止時間  250 ns
  $stop;
end


endmodule