DE2-115 Ckock50MHz converted to 1Hz Clock

DE2-115  Ckock50MHz converted to 1Hz Clock 

//需 Import  pin assignments  DE2_115_pin_assignments

KEY[0] = Reset 
LEDG[0]=1HZ 輸出

// Ch10 clk_1Hz.v
// 由 50M Hz 除頻至 1 Hz
//需 Import  pin assignments  DE2_115_pin_assignments
module CLK_1HZ(
  input  CLOCK_50, // 50 MHz clock
  input  [3:0] KEY,      // Pushbutton[3:0]
  input  [17:0] SW, // Toggle Switch[17:0]
  output [8:0] LEDG,  // LED Green
  output [17:0] LEDR   // LED Red
);

assign LEDR=SW;

// Setup clock divider
wire [6:0] myclock;
clk_div (CLOCK_50,KEY[0],myclock);
assign LEDG[0]=myclock[0];

endmodule




module clk_div (Clk50M,Clr,Clock);
input  Clk50M,Clr; // 一位元輸入
output Clock;
wire   Clk_1M,Clk_100K,Clk_10K,Clk_1K,
       Clk_100,Clk_10,Clk_1; // 一位元輸出
assign Clock = {Clk_1M,Clk_100K,Clk_10K,Clk_1K,
                Clk_100,Clk_10,Clk_1};
div50 D1 (Clk50M  , Clr, Clk_1M  );
div10 D2 (Clk_1M  , Clr, Clk_100K);
div10 D3 (Clk_100K, Clr, Clk_10K );
div10 D4 (Clk_10K , Clr, Clk_1K  );
div10 D5 (Clk_1K  , Clr, Clk_100 );
div10 D6 (Clk_100 , Clr, Clk_10  );
div10 D7 (Clk_10  , Clr, Clk_1   );

endmodule

module div50(CLK,RST,Q);

input CLK, RST;

output reg Q;

reg [4:0] count;

always @ (posedge CLK or negedge RST)

 begin

  if (~RST)

   begin

    Q <= 1'b0;

    count <= 5'b00000;

   end

  else if (count < 24)

   begin 

     count <= count+1'b1;

   end

  else 

   begin

    count <= 5'b00000;

    Q <= ~Q;

   end

 end

endmodule

// Ch10 div10.v

// 除頻 /10

module div10 (Clk_i,Clr,Clk_o);

input  Clk_i,Clr; // 一位元輸入

output reg Clk_o; // 一位元輸出宣告為暫存器資料

// MOD-10 (BCD) 除頻

reg [2:0] count;

always @ (posedge Clk_i or negedge Clr)

 begin

  if (~Clr)

   begin

    Clk_o <= 1'b0;

    count <= 3'b000;

   end

  else if (count < 4)

   begin 

     count <= count+1'b1;

   end

  else 

   begin

    count <= 3'b000;

    Clk_o <= ~Clk_o;

   end

 end

endmodule