數位IC設計入門-Verilog Sequential logic Serial in Serial Out Shift register Behavioral Modeling (& Test Bench)

數位IC設計入門-Verilog Sequential logic
Serial in Serial Out Shift register  Behavioral Modeling (& Test Bench)

//=======================================================
//數位IC設計入門-Verilog Sequential logic
//Serial in Serial Out Shift register  Behavioral Modeling (& Test Bench)
//File Name：SISO_Shift_Register.v
module SISO_Shift_Register (clock, clear, in, out);
input clock, clear, in;
output out;

reg [3:0] register;

always @(posedge clock)
begin
      if (clear)
      begin
            register = 4'd0;
      end
        
      else
      begin
            register[3] = register[2];
            register[2] = register[1];
            register[1] = register[0];
            register[0] = in;
      end
end

assign out = register[3];

endmodule

//======================================================= // 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps    
module Test_bench;
 //module SISO_Shift_Register (clock, clear, in, out);
 //input clock, clear, in;
 //output out;

// Inputs
 reg clock=0, clear=1, in=0;

// Outputs
wire out;


// Instantiate the Unit Under Test (UUT)
// SISO_Shift_Register (clock, clear, in, out);

SISO_Shift_Register  UUT (clock, clear, in, out);

initial begin
  $monitor(clock, clear, in, out);
  // Initialize Inputs
  #5 clear=0;
  #15 in=1;
  #25 in=0;
  #35 in=1;
  #25 in=0;
  #25 in=1;
  #25 in=0;
end

always #10 clock= ~clock;  

initial
begin
  #150;   // 模擬終止時間  250 ns
  $stop;
end
endmodule
//=======================================================