Verilog 應用範例 : 按鍵防彈跳適用於DE2-115 (DE2-70)
程式( 防彈跳 )：
module KEY_Debounce( CLK, RST, KEY_In, KEY_Out );
parameter DeB_Num = 4; // 取樣次數
parameter DeB_SET = 4'b0000; // 設置
parameter DeB_RST = 4'b1111; // 重置
input CLK, RST;
input KEY_In;
output KEY_Out;
reg KEY_Out = 1'b1;
reg [DeB_Num-1:0] Bounce = 4'b1111; // 初始化
always @( posedge CLK, negedge RST ) begin // 一次約200Hz 5ms
if( !RST )
Bounce <= DeB_RST; // Bounce重置
else begin // 取樣4次
integer i;
Bounce[0] <= KEY_In;
for( i=0; i<DeB_Num-1; i=i+1 )
Bounce[i+1] <= Bounce[i];
end
case( Bounce )
DeB_SET: KEY_Out <= 1'b0;
default: KEY_Out <= 1'b1;
endcase
end
endmodule
module KEY_Debounce( CLK, RST, KEY_In, KEY_Out );
parameter DeB_Num = 4; // 取樣次數
parameter DeB_SET = 4'b0000; // 設置
parameter DeB_RST = 4'b1111; // 重置
input CLK, RST;
input KEY_In;
output KEY_Out;
reg KEY_Out = 1'b1;
reg [DeB_Num-1:0] Bounce = 4'b1111; // 初始化
always @( posedge CLK, negedge RST ) begin // 一次約200Hz 5ms
if( !RST )
Bounce <= DeB_RST; // Bounce重置
else begin // 取樣4次
integer i;
Bounce[0] <= KEY_In;
for( i=0; i<DeB_Num-1; i=i+1 )
Bounce[i+1] <= Bounce[i];
end
case( Bounce )
DeB_SET: KEY_Out <= 1'b0;
default: KEY_Out <= 1'b1;
endcase
end
endmodule
//適用於DE2-115
module Key_Debunce(
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [8:0] LEDG, // LED Green
output [17:0] LEDR // LED Red
);
// Setup clock divider
wire [6:0] myclock;
/*
divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
*/
clock_divider cdiv(CLOCK_50,KEY[3],myclock); //Reset KEY[3]
assign LEDG[7]=myclock[0]; //for debug
wire Ko1,Ko2;
KEY_Debounce u1(myclock[2],KEY[0],Ko1);
KEY_Debounce u2(myclock[2],SW[8],Ko2);
//assign LEDG[0]=KEY[0];
assign LEDR[0]=Ko1;
assign LEDR[8]=Ko2;
endmodule
module KEY_Debounce( CLK, KEY_In, KEY_Out );
parameter DeB_Num = 4; // 取樣次數
parameter DeB_SET = 4'b0000; // 設置
parameter DeB_RST = 4'b1111; // 重置
input CLK; //CLK 一次約200Hz 5ms
input KEY_In;
output KEY_Out;
reg KEY_Out = 1'b1;
reg [DeB_Num-1:0] Bounce = 4'b1111; // 初始化
always @( posedge CLK) begin // 一次約200Hz 5ms
integer i; // 取樣4次
Bounce[0] <= KEY_In;
for( i=0; i<DeB_Num-1; i=i+1 )
Bounce[i+1] <= Bounce[i];
case( Bounce )
DeB_SET: KEY_Out <= 1'b0;
default: KEY_Out <= 1'b1;
endcase
end
endmodule
module clock_divider(CLK,RST,clock);
input CLK,RST;
output [6:0] clock;
wire clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz;
assign clock = {clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz};
divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
endmodule
module divide_by_10(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [2:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 3'b000;
end
else if (count < 4)
begin
count <= count+1'b1;
end
else
begin
count <= 3'b000;
Q <= ~Q;
end
end
endmodule
module divide_by_50(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [4:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 5'b00000;
end
else if (count < 24)
begin
count <= count+1'b1;
end
else
begin
count <= 5'b00000;
Q <= ~Q;
end
end
endmodule
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