DE2-115 Key Debounce

DE2-115  Key Debounce

//需 Import  pin assignments  DE2_115_pin_assignments

// Ch10 debounce1.v
// 去彈跳電路 1
//需 Import  pin assignments  DE2_115_pin_assignments
module Deb(
  input  CLOCK_50, // 50 MHz clock
  input  [3:0] KEY,      // Pushbutton[3:0]
  input  [17:0] SW, // Toggle Switch[17:0]
  output [8:0] LEDG,  // LED Green
  output [17:0] LEDR   // LED Red
 );

// Setup clock divider
wire [6:0] myclock;
/*
 divide_by_50 d6(clk_1Mhz,CLK,RST);
 divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
 divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
 divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
 divide_by_10 d2(clk_100hz,clk_1Khz,RST);
 divide_by_10 d1(clk_10hz,clk_100hz,RST);
 divide_by_10 d0(clk_1hz,clk_10hz,RST);
*/
 clock_divider cdiv(CLOCK_50,KEY[3],myclock);
 assign LEDR[0]=myclock[0]; //for debug
 assign LEDR[1]=myclock[1]; //for debug
 assign LEDR[2]=myclock[2]; //for debug
 assign LEDR[3]=myclock[3]; //for debug
 assign LEDR[4]=myclock[4]; //for debug
 assign LEDR[5]=myclock[5]; //for debug
 assign LEDR[6]=myclock[6]; //for debug


 wire [3:1]Ko;
 debounce1 (myclock[2],KEY[0],Ko[1],Ko[2],Ko[3]);
 assign LEDG[0]=KEY[0];
 assign LEDG[1]=Ko[1];
 assign LEDG[2]=Ko[2];
 assign LEDG[3]=Ko[3];

 endmodule



// Ch10 debounce1.v
// 去彈跳電路 1

module debounce1 (Clk100,Ki,Ko1,Ko2,Ko3);
input  Clk100,Ki; // 一位元輸入
output Ko1,Ko2,Ko3; // 一位元輸出
reg    Ko1,Ko2,Ko3; // 宣告為暫存器資料
reg    [2:0] Q; // 宣告為暫存器資料

// 取樣頻率約 100 Hz, 連續取樣三次
always@ (posedge Clk100)
  begin
    Q[2] = Q[1];
    Q[1] = Q[0];
    Q[0] = Ki;
  end

// 產生去彈跳信號
always@ (Q)
  begin
    if (Q == 3'b111) // 前後緣
      Ko1 = 1;
    else
      Ko1 = 0;
    if (Q == 3'b001) // 前緣
      Ko2 = 1;
    else
      Ko2 = 0;
    if (Q == 3'b110) // 後緣
      Ko3 = 1;
    else
      Ko3 = 0;
  end

endmodule


module clock_divider(CLK,RST,clock);
input CLK,RST;
output [6:0] clock;
wire clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz;

assign clock = {clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz};

divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
endmodule

module divide_by_10(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [2:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 3'b000;
end
else if (count < 4)
begin
count <= count+1'b1;
end
else
begin
count <= 3'b000;
Q <= ~Q;
end
end
endmodule

module divide_by_50(Q,CLK,RST);

input CLK, RST;

output Q;

reg Q;

reg [4:0] count;

always @ (posedge CLK or negedge RST)

begin

if (~RST)

begin

Q <= 1'b0;

count <= 5'b00000;

end

else if (count < 24)

begin 

count <= count+1'b1;

end

else 

begin

count <= 5'b00000;

Q <= ~Q;

end

end

endmodule