顯示一條 「蛇」，再一排 （四個）七段顯示器上以8字形繞圈，「蛇」的形狀為七段顯示器上顯示出「連續」3條亮線，以
a0a1a2 --> a1a2a3 --> a2a3b3 --> a3b3g3--> b3g3g2 -->g3g2g1...
輸入clock ,
SW[0] === reset 回到a0a1a2初始狀態 ,
SW[1] === turn =0 順時針 , =1逆時針方向
// 需 Import pin assignments DE2_115_pin_assignments
// Verilog 硬體描述語言 HDL
// Ch08 RunSnake 移動蛇 蛇行燈run snake
//=====================================================
module run_snake(
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR // LED Red
);
// blank unused 7-segment digits
//assign HEX0 = 7'b111_1111;
//assign HEX1 = 7'b111_1111;
//assign HEX2 = 7'b111_1111;
//assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;
// Setup clock divider
wire [6:0] myclock;
/*
divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
*/
clock_divider clkdiv(CLOCK_50,KEY[3],myclock);
assign LEDG[4]=myclock[0];
assign LEDG[3:0]=KEY[3:0];
assign LEDR=SW;
//module clock_divider(CLK,RST,clock);
runsnakeModule (myclock[0],SW[0],SW[1],HEX3,HEX2,HEX1,HEX0);
endmodule
module runsnakeModule (clk,reset,trun,seg7_1,seg7_2,seg7_3,seg7_4);
input clk,reset,trun;
output reg[6:0] seg7_1,seg7_2,seg7_3,seg7_4;
reg [4:0]CS=5'd0;
reg [4:0]NS=5'd0;
parameter INITAL_STATE=5'd0;
always @(posedge clk or negedge reset) begin
if (~reset) begin
CS <= INITAL_STATE;
end
else begin
CS <= NS;
end
end
always @(CS or trun) begin
if (trun) begin
if (CS == INITAL_STATE)
NS = 5'd19;
else
NS= CS -1;
end else begin
if (CS == 5'd19)
NS = INITAL_STATE;
else
NS = CS +1;
end
end
always @(CS) begin
case (CS)
INITAL_STATE: begin
seg7_1=~8'b0000_0001;
seg7_2=~8'b0000_0001;
seg7_3=~8'b0000_0001;
seg7_4=~8'b0000_0000;
end
1: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0001;
seg7_3=~8'b0000_0001;
seg7_4=~8'b0000_0001;
end
2: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_0001;
seg7_4=~8'b0000_0011;
end
3: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0100_0011;
end
4: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0100_0000;
seg7_4=~8'b0100_0010;
end
5: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0100_0000;
seg7_3=~8'b0100_0000;
seg7_4=~8'b0100_0000;
end
6: begin
seg7_1=~8'b0100_0000;
seg7_2=~8'b0100_0000;
seg7_3=~8'b0100_0000;
seg7_4=~8'b0000_0000;
end
7: begin
seg7_1=~8'b0101_0000;
seg7_2=~8'b0100_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
8: begin
seg7_1=~8'b0101_1000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
9: begin
seg7_1=~8'b0001_1000;
seg7_2=~8'b0000_1000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
10: begin
seg7_1=~8'b0000_1000;
seg7_2=~8'b0000_1000;
seg7_3=~8'b0000_1000;
seg7_4=~8'b0000_0000;
end
11: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_1000;
seg7_3=~8'b0000_1000;
seg7_4=~8'b0000_1000;
end
12: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_1000;
seg7_4=~8'b0000_1100;
end
13: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0100_1100;
end
14: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0100_0000;
seg7_4=~8'b0100_0100;
end
15: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0100_0000;
seg7_3=~8'b0100_0000;
seg7_4=~8'b0100_0000;
end
16: begin
seg7_1=~8'b0100_0000;
seg7_2=~8'b0100_0000;
seg7_3=~8'b0100_0000;
seg7_4=~8'b0000_0000;
end
17: begin
seg7_1=~8'b0110_0000;
seg7_2=~8'b0100_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
18: begin
seg7_1=~8'b0110_0001;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
19: begin
seg7_1=~8'b0010_0001;
seg7_2=~8'b0000_0001;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
default: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
endcase
end
endmodule
//=====================================================
// Clock 50 MH divide to 7 clock
//=====================================================
module clock_divider(CLK,RST,clock);
input CLK,RST;
output [6:0] clock;
wire clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz;
assign clock = {clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz};
divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
endmodule
module divide_by_10(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [2:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 3'b000;
end
else if (count < 4)
begin
count <= count+1'b1;
end
else
begin
count <= 3'b000;
Q <= ~Q;
end
end
endmodule
module divide_by_50(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [4:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 5'b00000;
end
else if (count < 24)
begin
count <= count+1'b1;
end
else
begin
count <= 5'b00000;
Q <= ~Q;
end
end
endmodule
//Update Current State To Green LED Show
//=====================================================
// Verilog 硬體描述語言 HDL
// Ch08 RunSnake 移動蛇 蛇行燈run snake
//=====================================================
module run_snake(
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR // LED Red
);
// blank unused 7-segment digits
//assign HEX0 = 7'b111_1111;
//assign HEX1 = 7'b111_1111;
//assign HEX2 = 7'b111_1111;
//assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;
// Setup clock divider
wire [6:0] myclock;
/*
divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
*/
clock_divider clkdiv(CLOCK_50,KEY[3],myclock);
assign LEDG[7]=myclock[0];
assign LEDR=SW;
//module clock_divider(CLK,RST,clock);
runsnakeModule (myclock[0],SW[0],SW[1],HEX3,HEX2,HEX1,HEX0,LEDG[4:0]);
endmodule
module runsnakeModule (clk,reset,trun,seg7_1,seg7_2,seg7_3,seg7_4,CS_LED);
input clk,reset,trun;
output reg[6:0] seg7_1,seg7_2,seg7_3,seg7_4;
output reg [4:0]CS_LED;
reg [4:0]CS=5'd0;
reg [4:0]NS=5'd0;
parameter INITAL_STATE=5'd0;
always @(posedge clk or negedge reset) begin
if (~reset) begin
CS <= INITAL_STATE;
end
else begin
CS <= NS;
CS_LED<= NS;
end
end
always @(CS or trun) begin
if (trun) begin
if (CS == INITAL_STATE)
NS = 5'd19;
else
NS= CS -1;
end else begin
if (CS == 5'd19)
NS = INITAL_STATE;
else
NS = CS +1;
end
end
always @(CS) begin
case (CS)
INITAL_STATE: begin
seg7_1=~8'b0000_0001;
seg7_2=~8'b0000_0001;
seg7_3=~8'b0000_0001;
seg7_4=~8'b0000_0000;
end
1: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0001;
seg7_3=~8'b0000_0001;
seg7_4=~8'b0000_0001;
end
2: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_0001;
seg7_4=~8'b0000_0011;
end
3: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0100_0011;
end
4: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0100_0000;
seg7_4=~8'b0100_0010;
end
5: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0100_0000;
seg7_3=~8'b0100_0000;
seg7_4=~8'b0100_0000;
end
6: begin
seg7_1=~8'b0100_0000;
seg7_2=~8'b0100_0000;
seg7_3=~8'b0100_0000;
seg7_4=~8'b0000_0000;
end
7: begin
seg7_1=~8'b0101_0000;
seg7_2=~8'b0100_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
8: begin
seg7_1=~8'b0101_1000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
9: begin
seg7_1=~8'b0001_1000;
seg7_2=~8'b0000_1000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
10: begin
seg7_1=~8'b0000_1000;
seg7_2=~8'b0000_1000;
seg7_3=~8'b0000_1000;
seg7_4=~8'b0000_0000;
end
11: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_1000;
seg7_3=~8'b0000_1000;
seg7_4=~8'b0000_1000;
end
12: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_1000;
seg7_4=~8'b0000_1100;
end
13: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0100_1100;
end
14: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0100_0000;
seg7_4=~8'b0100_0100;
end
15: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0100_0000;
seg7_3=~8'b0100_0000;
seg7_4=~8'b0100_0000;
end
16: begin
seg7_1=~8'b0100_0000;
seg7_2=~8'b0100_0000;
seg7_3=~8'b0100_0000;
seg7_4=~8'b0000_0000;
end
17: begin
seg7_1=~8'b0110_0000;
seg7_2=~8'b0100_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
18: begin
seg7_1=~8'b0110_0001;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
19: begin
seg7_1=~8'b0010_0001;
seg7_2=~8'b0000_0001;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
default: begin
seg7_1=~8'b0000_0000;
seg7_2=~8'b0000_0000;
seg7_3=~8'b0000_0000;
seg7_4=~8'b0000_0000;
end
endcase
end
endmodule
沒有留言:
張貼留言