LFSR Linear Feedback Shift Register

LFSR   Linear Feedback Shift Register

// 需 Import  pin assignments  DE2_115_pin_assignments

//=====================================================
// Verilog 硬體描述語言 HDL
// Ch08 RLinear Feedback Shift Register LFSR
//=====================================================
module LFSR(
  input  CLOCK_50, // 50 MHz clock
  input  [3:0] KEY,      // Pushbutton[3:0]
  input  [17:0] SW, // Toggle Switch[17:0]
  output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7,  // Seven Segment Digits
  output [8:0] LEDG,  // LED Green
  output [17:0] LEDR   // LED Red
 );
 // blank unused 7-segment digits
//assign HEX0 = 7'b111_1111;
//assign HEX1 = 7'b111_1111;
//assign HEX2 = 7'b111_1111;
assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;

wire [7:0] segout0;   //HEX 0
wire [7:0] segout1;   //HEX 1
wire [7:0] segout2;   //HEX 2
//wire [7:0] segout3;   //HEX 3
// Setup clock divider
wire [6:0] myclock;

/*
 divide_by_50 d6(clk_1Mhz,CLK,RST);
 divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
 divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
 divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
 divide_by_10 d2(clk_100hz,clk_1Khz,RST);
 divide_by_10 d1(clk_10hz,clk_100hz,RST);
 divide_by_10 d0(clk_1hz,clk_10hz,RST);
*/
 clock_divider clkdiv(CLOCK_50,KEY[3],myclock);

 //module clock_divider(CLK,RST,clock);
 parameter c_NUM_BITS = 7;

 wire [c_NUM_BITS-1:0]oLFSR;

 assign  LEDG[c_NUM_BITS-1:0]=oLFSR;

 LFSR_test #(.NUM_BITS(c_NUM_BITS)) LFSR_inst
         (.i_Clk(myclock[2]),
          .i_Enable(myclock[0]),
          //.i_Enable(KEY[0]),
          
          .i_Seed_DV(SW[0]),
          .i_Seed_Data({c_NUM_BITS{1'b0}}), // Replication
          .o_LFSR_Data(oLFSR),
          .o_LFSR_Done(LEDG[7])
          );
 // ====================================
 //input [7:0] A;
 //output [3:0] ONES, TENS;
 //output [1:0] HUNDREDS;
wire[3:0] ones, tens;
wire[1:0] hundreds; 
binary_to_BCD(oLFSR,ones,tens,hundreds);

hex_7seg u1(ones,segout0);
hex_7seg u2(tens,segout1);
hex_7seg u3(hundreds,segout2);

//input [3:0] hex_digit;
//output [6:0] seg;

assign HEX0=segout0;
assign HEX1=segout1;
assign HEX2=segout2;

endmodule


///////////////////////////////////////////////////////////////////////////////
// File downloaded from http://www.nandland.com
///////////////////////////////////////////////////////////////////////////////
// Description: 
// A LFSR or Linear Feedback Shift Register is a quick and easy way to generate
// pseudo-random data inside of an FPGA.  The LFSR can be used for things like
// counters, test patterns, scrambling of data, and others.  This module
// creates an LFSR whose width gets set by a parameter.  The o_LFSR_Done will
// pulse once all combinations of the LFSR are complete.  The number of clock
// cycles that it takes o_LFSR_Done to pulse is equal to 2^g_Num_Bits-1.  For
// example setting g_Num_Bits to 5 means that o_LFSR_Done will pulse every
// 2^5-1 = 31 clock cycles.  o_LFSR_Data will change on each clock cycle that
// the module is enabled, which can be used if desired.
//
// Parameters:
// NUM_BITS - Set to the integer number of bits wide to create your LFSR.
///////////////////////////////////////////////////////////////////////////////
module LFSR_test #(parameter NUM_BITS)
  (
   input i_Clk,
   input i_Enable,

   // Optional Seed Value
   input i_Seed_DV,
   input [NUM_BITS-1:0] i_Seed_Data,

   output [NUM_BITS-1:0] o_LFSR_Data,
   output o_LFSR_Done
   );
   
  reg [NUM_BITS:1] r_LFSR = 0;
  reg              r_XNOR;


  // Purpose: Load up LFSR with Seed if Data Valid (DV) pulse is detected.
  // Othewise just run LFSR when enabled.
  always @(posedge i_Clk)
    begin
      if (i_Enable == 1'b1)
        begin
          if (i_Seed_DV == 1'b1)
            r_LFSR <= i_Seed_Data;
          else
            r_LFSR <= {r_LFSR[NUM_BITS-1:1], r_XNOR};
        end
    end

  // Create Feedback Polynomials.  Based on Application Note:
  // http://www.xilinx.com/support/documentation/application_notes/xapp052.pdf
  always @(*)
    begin
      case (NUM_BITS)
        3: begin
          r_XNOR = r_LFSR[3] ^~ r_LFSR[2];
        end
        4: begin
          r_XNOR = r_LFSR[4] ^~ r_LFSR[3];
        end
        5: begin
          r_XNOR = r_LFSR[5] ^~ r_LFSR[3];
        end
        6: begin
          r_XNOR = r_LFSR[6] ^~ r_LFSR[5];
        end
        7: begin
          r_XNOR = r_LFSR[7] ^~ r_LFSR[6];
        end
        8: begin
          r_XNOR = r_LFSR[8] ^~ r_LFSR[6] ^~ r_LFSR[5] ^~ r_LFSR[4];
        end
        9: begin
          r_XNOR = r_LFSR[9] ^~ r_LFSR[5];
        end
        10: begin
          r_XNOR = r_LFSR[10] ^~ r_LFSR[7];
        end
        11: begin
          r_XNOR = r_LFSR[11] ^~ r_LFSR[9];
        end
        12: begin
          r_XNOR = r_LFSR[12] ^~ r_LFSR[6] ^~ r_LFSR[4] ^~ r_LFSR[1];
        end
        13: begin
          r_XNOR = r_LFSR[13] ^~ r_LFSR[4] ^~ r_LFSR[3] ^~ r_LFSR[1];
        end
        14: begin
          r_XNOR = r_LFSR[14] ^~ r_LFSR[5] ^~ r_LFSR[3] ^~ r_LFSR[1];
        end
        15: begin
          r_XNOR = r_LFSR[15] ^~ r_LFSR[14];
        end
        16: begin
          r_XNOR = r_LFSR[16] ^~ r_LFSR[15] ^~ r_LFSR[13] ^~ r_LFSR[4];
          end
        17: begin
          r_XNOR = r_LFSR[17] ^~ r_LFSR[14];
        end
        18: begin
          r_XNOR = r_LFSR[18] ^~ r_LFSR[11];
        end
        19: begin
          r_XNOR = r_LFSR[19] ^~ r_LFSR[6] ^~ r_LFSR[2] ^~ r_LFSR[1];
        end
        20: begin
          r_XNOR = r_LFSR[20] ^~ r_LFSR[17];
        end
        21: begin
          r_XNOR = r_LFSR[21] ^~ r_LFSR[19];
        end
        22: begin
          r_XNOR = r_LFSR[22] ^~ r_LFSR[21];
        end
        23: begin
          r_XNOR = r_LFSR[23] ^~ r_LFSR[18];
        end
        24: begin
          r_XNOR = r_LFSR[24] ^~ r_LFSR[23] ^~ r_LFSR[22] ^~ r_LFSR[17];
        end
        25: begin
          r_XNOR = r_LFSR[25] ^~ r_LFSR[22];
        end
        26: begin
          r_XNOR = r_LFSR[26] ^~ r_LFSR[6] ^~ r_LFSR[2] ^~ r_LFSR[1];
        end
        27: begin
          r_XNOR = r_LFSR[27] ^~ r_LFSR[5] ^~ r_LFSR[2] ^~ r_LFSR[1];
        end
        28: begin
          r_XNOR = r_LFSR[28] ^~ r_LFSR[25];
        end
        29: begin
          r_XNOR = r_LFSR[29] ^~ r_LFSR[27];
        end
        30: begin
          r_XNOR = r_LFSR[30] ^~ r_LFSR[6] ^~ r_LFSR[4] ^~ r_LFSR[1];
        end
        31: begin
          r_XNOR = r_LFSR[31] ^~ r_LFSR[28];
        end
        32: begin
          r_XNOR = r_LFSR[32] ^~ r_LFSR[22] ^~ r_LFSR[2] ^~ r_LFSR[1];
        end

      endcase // case (NUM_BITS)
    end // always @ (*)


  assign o_LFSR_Data = r_LFSR[NUM_BITS:1];

  // Conditional Assignment (?)
  assign o_LFSR_Done = (r_LFSR[NUM_BITS:1] == i_Seed_Data) ? 1'b1 : 1'b0;

endmodule // LFSR

//======================================
module binary_to_BCD(A,ONES,TENS,HUNDREDS);
input [7:0] A;
output [3:0] ONES, TENS;
output [1:0] HUNDREDS;

wire [3:0] c1,c2,c3,c4,c5,c6,c7;
wire [3:0] d1,d2,d3,d4,d5,d6,d7;

assign d1 = {1'b0,A[7:5]};
assign d2 = {c1[2:0],A[4]};
assign d3 = {c2[2:0],A[3]};
assign d4 = {c3[2:0],A[2]};
assign d5 = {c4[2:0],A[1]};
assign d6 = {1'b0,c1[3],c2[3],c3[3]};
assign d7 = {c6[2:0],c4[3]};
add3 m1(d1,c1);
add3 m2(d2,c2);
add3 m3(d3,c3);
add3 m4(d4,c4);
add3 m5(d5,c5);
add3 m6(d6,c6);
add3 m7(d7,c7);
assign ONES = {c5[2:0],A[0]};
assign TENS = {c7[2:0],c5[3]};
assign HUNDREDS = {c6[3],c7[3]};

endmodule


module add3(in,out);
input [3:0] in;
output [3:0] out;
reg [3:0] out;

always @ (in)
 case (in)
 4'b0000: out <= 4'b0000;
 4'b0001: out <= 4'b0001;
 4'b0010: out <= 4'b0010;
 4'b0011: out <= 4'b0011;
 4'b0100: out <= 4'b0100;
 4'b0101: out <= 4'b1000;
 4'b0110: out <= 4'b1001;
 4'b0111: out <= 4'b1010;
 4'b1000: out <= 4'b1011;
 4'b1001: out <= 4'b1100;
 default: out <= 4'b0000;
 endcase
endmodule
//======================================
//++++++++++++++++++++++++++++++++++++++
 module hex_7seg(hex_digit,seg);
input [3:0] hex_digit;
output [6:0] seg;
reg [6:0] seg;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off

always @ (hex_digit)
case (hex_digit)
  4'h0: seg = 7'b1000000;
  4'h1: seg = 7'b1111001;  // ---a----
  4'h2: seg = 7'b0100100;  // |   |
  4'h3: seg = 7'b0110000;  // f   b
  4'h4: seg = 7'b0011001;  // |   |
  4'h5: seg = 7'b0010010;  // ---g----
  4'h6: seg = 7'b0000010;  // |   |
  4'h7: seg = 7'b1111000;  // e   c
  4'h8: seg = 7'b0000000;  // |   |
  4'h9: seg = 7'b0011000;  // ---d----
  4'ha: seg = 7'b0001000;
  4'hb: seg = 7'b0000011;
  4'hc: seg = 7'b1000110;
  4'hd: seg = 7'b0100001;
  4'he: seg = 7'b0000110;
  4'hf: seg = 7'b0001110;
endcase
endmodule

//++++++++++++++++++++++++++++++++++++++

module clock_divider(CLK,RST,clock);
 input CLK,RST;
 output [6:0] clock;
 wire clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz;

 assign clock = {clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz};

 divide_by_50 d6(clk_1Mhz,CLK,RST);
 divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
 divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
 divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
 divide_by_10 d2(clk_100hz,clk_1Khz,RST);
 divide_by_10 d1(clk_10hz,clk_100hz,RST);
 divide_by_10 d0(clk_1hz,clk_10hz,RST);
endmodule

module divide_by_10(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [2:0] count;
always @ (posedge CLK or negedge RST)
 begin
  if (~RST)
   begin
    Q <= 1'b0;
    count <= 3'b000;
   end
  else if (count < 4)
   begin 
     count <= count+1'b1;
   end
  else 
   begin
    count <= 3'b000;
    Q <= ~Q;
   end
 end
endmodule

module divide_by_50(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [4:0] count;
always @ (posedge CLK or negedge RST)
 begin
  if (~RST)
   begin
    Q <= 1'b0;
    count <= 5'b00000;
   end
  else if (count < 24)
   begin 
     count <= count+1'b1;
   end
  else 
   begin
    count <= 5'b00000;
    Q <= ~Q;
   end
 end

endmodule