數位IC設計入門-Verilog combinational logic Ripple Carry 4bit Adder全加器 Behavioral Modeling Hierarchical_RP_ADDER（Test Bench）

數位IC設計入門-Verilog combinational logic Ripple Carry 4bit Adder全加器 Behavioral Modeling Hierarchical_RP_ADDER（Test Bench）


  //數位IC設計入門-Verilog combinational logic Ripple Carry 4bit Adder全加器 Behavioral Modeling Hierarchical_RP_ADDER（Test Bench）
  module Hierarchical_RP_ADDER(a, b, c_in, sum, cy);
  input [3:0] a, b;
  input c_in;
  output [3:0] sum;
  output cy;
  wire w0, w1, w2;

  Full_Adder FA0(a[0], b[0], c_in, sum[0],  w0);
  Full_Adder FA1(a[1], b[1], w0  , sum[1],  w1);
  Full_Adder FA2(a[2], b[2], w1  , sum[2],  w2);
  Full_Adder FA3(a[3], b[3], w2  , sum[3],  cy);

  endmodule

  module Full_Adder(a, b, c_in, sum, cy);
  input a, b, c_in;
  output sum, cy;
  reg sum, cy;

  always@(a or b or c_in)
  begin
        {cy, sum} = a + b + c_in;
  end

  endmodule

// 時間單位 100ns, 時間精確度100 ps
`timescale 100ns/100ps    
module Test_bench;
  //module FA (a, b, c, sum, cy);
  //input a, b, c;
  //output sum, cy;

// Inputs
reg [3:0]a=0;
reg [3:0]b=0;
reg c_in=0;

// Outputs
wire [3:0]sum;
wire cy;

// Instantiate the Unit Under Test (UUT)
//module FA (a, b, c, sum, cy);

Hierarcjical_RP_ADDER UUT(a, b,c_in, sum, cy);

initial begin
 $monitor(a, b,c_in, sum, cy);
    // Initialize Inputs
 #25 a[3:0]=4'h0 ; b[3:0]=4'h0 ;c_in=1'b1; 
 #25 a[3:0]=4'hA ; b[3:0]=4'h9 ;c_in=1'b0; 
 #25 a[3:0]=4'h5 ; b[3:0]=4'hA ;c_in=1;
 #25 a[3:0]=4'h5 ; b[3:0]=4'h8 ;c_in=0;
 #25 a[3:0]=4'h2 ; b[3:0]=4'h6 ;c_in=1;
 #25 a[3:0]=4'h7 ; b[3:0]=4'hf ;c_in=0;
 #25 a[3:0]=4'hf ; b[3:0]=4'hf ;c_in=1;

end

initial
begin
  #200;   // 模擬終止時間  200 ns
  $stop;
end

endmodule