Ch08 cnt1.v 上數與下數計數器
//需 Import pin assignments DE2_115_pin_assignments
//=====================================================
//需 Import pin assignments DE2_115_pin_assignments
//Verilog 硬體描述語言 HDL
// Ch08 cnt1.v
// 上數與下數計數器
//=====================================================
module UP_DN_CNT4bit (
input CLOCK_50, // 50 MHz clock
input [3:0] KEY, // Pushbutton[3:0]
input [17:0] SW, // Toggle Switch[17:0]
output [6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7, // Seven Segment Digits
output [8:0] LEDG, // LED Green
output [17:0] LEDR // LED Red
);
// blank unused 7-segment digits
//assign HEX0 = 7'b111_1111;
assign HEX1 = 7'b111_1111;
assign HEX2 = 7'b111_1111;
//assign HEX3 = 7'b111_1111;
assign HEX4 = 7'b111_1111;
assign HEX5 = 7'b111_1111;
assign HEX6 = 7'b111_1111;
assign HEX7 = 7'b111_1111;
assign LEDR=SW;
// Setup clock divider
wire [6:0] myclock;
/*
divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
*/
clock_divider cdiv(CLOCK_50,KEY[3],myclock);
//module clock_divider(CLK,RST,clock);
cnt1 (myclock[0],KEY[0],LEDG[3:0],LEDG[7:4]);
//module cnt1 (Clk,Clr,Q1,Q2);
//input Clk,Clr; // 一位元輸入
//output [3:0] Q1,Q2; // 四位元輸出
hex_7seg u1(LEDG[3:0],HEX0);
hex_7seg u2(LEDG[7:4],HEX3);
endmodule
//=====================================================
//Verilog 硬體描述語言 HDL
// Ch08 cnt1.v
// 上數與下數計數器
module cnt1 (Clk,Clr,Q1,Q2);
input Clk,Clr; // 一位元輸入
output [3:0] Q1,Q2; // 四位元輸出
reg [3:0] Q1,Q2; // 宣告為暫存器資料
// 上緣觸發時脈, 上緣同步清除, 上數計數器
always@ (posedge Clk)
if (!Clr) Q1 = 0; //DE2-115 KEY[3:0] = Normal Hi change Clr-->(!Clr)
else Q1 = Q1 + 1;
// 上緣觸發時脈, 上緣同步清除, 減二下數計數器
always@ (posedge Clk)
if (!Clr) Q2 = 15;
else Q2 = Q2 - 2;
endmodule
//=====================================================
module clock_divider(CLK,RST,clock);
input CLK,RST;
output [6:0] clock;
wire clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz;
assign clock = {clk_1Mhz,clk_100Khz,clk_10Khz,clk_1Khz,clk_100hz,clk_10hz,clk_1hz};
divide_by_50 d6(clk_1Mhz,CLK,RST);
divide_by_10 d5(clk_100Khz,clk_1Mhz,RST);
divide_by_10 d4(clk_10Khz,clk_100Khz,RST);
divide_by_10 d3(clk_1Khz,clk_10Khz,RST);
divide_by_10 d2(clk_100hz,clk_1Khz,RST);
divide_by_10 d1(clk_10hz,clk_100hz,RST);
divide_by_10 d0(clk_1hz,clk_10hz,RST);
endmodule
//=====================================================
module divide_by_10(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [2:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 3'b000;
end
else if (count < 4)
begin
count <= count+1'b1;
end
else
begin
count <= 3'b000;
Q <= ~Q;
end
end
endmodule
//=====================================================
module divide_by_50(Q,CLK,RST);
input CLK, RST;
output Q;
reg Q;
reg [4:0] count;
always @ (posedge CLK or negedge RST)
begin
if (~RST)
begin
Q <= 1'b0;
count <= 5'b00000;
end
else if (count < 24)
begin
count <= count+1'b1;
end
else
begin
count <= 5'b00000;
Q <= ~Q;
end
end
endmodule
//=====================================================
//++++++++++++++++++++++++++++++++++++++
module hex_7seg(hex_digit,seg);
input [3:0] hex_digit;
output [6:0] seg;
reg [6:0] seg;
// seg = {g,f,e,d,c,b,a};
// 0 is on and 1 is off
always @ (hex_digit)
case (hex_digit)
4'h0: seg = 7'b1000000;
4'h1: seg = 7'b1111001; // ---a----
4'h2: seg = 7'b0100100; // | |
4'h3: seg = 7'b0110000; // f b
4'h4: seg = 7'b0011001; // | |
4'h5: seg = 7'b0010010; // ---g----
4'h6: seg = 7'b0000010; // | |
4'h7: seg = 7'b1111000; // e c
4'h8: seg = 7'b0000000; // | |
4'h9: seg = 7'b0011000; // ---d----
4'ha: seg = 7'b0001000;
4'hb: seg = 7'b0000011;
4'hc: seg = 7'b1000110;
4'hd: seg = 7'b0100001;
4'he: seg = 7'b0000110;
4'hf: seg = 7'b0001110;
endcase
endmodule
//++++++++++++++++++++++++++++++++++++++
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