Verilog HDL: User-Defined Primitives(UDP)

源自http://asic-soc.blogspot.tw/2012/06/verilog-hdl-user-defined-primitivesudp.html

Verilog HDL: User-Defined Primitives(UDP)

User-Defined  Primitives(UDP) :

• One of the advanced concepts in verilog
• non synthesizable
• single output many iput
• consume very less memory
• I/Os must be scalar (i.e. bit)
• ‘z’ value is not supported.

primitive myprimitive(c,a,b)

input a,b;

output c;

table

0 0:0

0 1:0

1 0:0

1 1:0

endtable

endprimitive

Syntax :

Primitive      //UDP  name  (only one allowed) and terminal list

(   //output_terminal -> only  one  allowed

    ) ;                                          

//terminal  declarations

output  ;

input  ;

reg  ;

initial    = ;

//UDP   state  table

table

                 entries>

endtable

//end  of  UDP definition

endprimitive

UDP  Rules  :

1)      UDPs  can take only scalar input terminals (1 bit). Multiple  input  terminals are permitted.

2)      UDPs  can  have only  one  scalar  output  terminal (1 bit).  The  output  terminal must  always  appear  first  in the terminal list. Multiple output terminals are not allowed.

3)      In the declarations section, the output terminal is declared with the keyword output. Since sequential UDPs store state, the output terminal must also be declared as a reg.

4)      The inputs are declared with the keyword input.

5)      The state in a sequential UDP can be initialized  with  an  ‘initial’ statement. This statement is optional. A 1-bit value is assigned to the output, which is declared as reg.

6)      The state table entries can contain values 0,1,or x .  UDPs  do not handle z values. Z  values passed  to a  UDP  are  treated  x  values.

7)      UDPs  are  defined  at the same level as  modules. UDPs  can not be defined inside modules. They can be  instantiated  only inside  modules. UDPs are instantiated exactly like gate  primitives.

8)      UDPs  do not  support  inout  ports.

Combinational  UDPs :

Eg : 

primitive   udp_and (out,a,b);

output  out;

input  a,b;

table 

             //a             b   : out

                --------------------

0              0  :  0;

0              1  :  0;

1              0  :  0;

1              1  :  1;

endtable

endprimitive

Sequential    UDPs  :

->the output of  a  sequential  UDP is  always  declared  as  a  reg.

->an  initial  statement  can  be  used  to  initialize  output  of  sequential  UDPs.

->the  format  of  a  state  table  using   entry  is  slightly  different 

        ……….. : : ;

->if  a  sequential  UDP is  sensitive  to   input levels, it is  called  a  level  sensitive sequential  UDP.

->if  a  sequential  UDP is  sensitive  to  edge  transition  on  inputs,  it  is  called  an  edge-sensitive  sequential  UDP.

Eg :

//Edge  triggered  T-FF

primitive  T-FF (output   reg  q,input  clk,clear);

//no  initialization  of  q;  T-FF  will  be  initialized  with clear signal.

table

       //clk          clear   :  q  :   q+ ;

            ?               1      :   ?  :  0 ;             //asynchronous  clear  condition

            ?            (10)    :   ?  :  - ;            //ignore  -ve  edge  of  clear

            (10)          0      :   1 :   0;            //toggle  FF  at  -ve  edge  of  clk

            (10)          0      :   0 :   1;

            (0?)          0      :    ? :   - ;       //ignore  +ve   edge  of  clock

endtable

endprimitive