2012年10月30日 星期二

適用於 DE2-70 P11-2 BCD Counter 0000-9999 BCD Counter

P11-2 0000-9999 BCD Counter 

module BCD9999(SW, LEDR, LEDG , CLOCK_50 ,KEY ,HEX0 ,HEX1 ,HEX2,HEX3 );

input  [17:0] SW; // toggle switches

input  [7:0] KEY;     // Push bottom
input  CLOCK_50; //Clock 27MHz , 50Mhz

output [17:0] LEDR; // red  LEDS   
  output [8:0] LEDG; // green LEDs
    
    output [6:0] HEX0,HEX1,HEX2,HEX3; //7-segment display
    
  
//set original program input , output 
  
//(clr,clk,q);
//input clr,clk;
//output [15:0]q;
wire clr,clk;
reg [15:0]q;
    wire HZ_1; //1HZ Clock

assign clr=KEY[0];
assign clk=CLOCK_50;


    wire [7:0] segout0;   //HEX 0
    wire [7:0] segout1;   //HEX 1
    wire [7:0] segout2;   //HEX 1
    wire [7:0] segout3;   //HEX 1
    


     //module _1HZ (CLK, RSTn, LED_Out);

     
     _1HZ UUT01 (.CLK(clk),
.RSTn(clr),
.LED_Out(HZ_1));

     

always @(posedge HZ_1 or negedge clr) 

begin
if(!clr) q[15:0]=0;
else if(q[15:0]==16'H9999) q[15:0]=0;
else if(q[11:0]==12'H999) q[15:0]=q[15:0]+12'H667;
else if(q[ 7:0]== 8'H99) q[15:0]=q[15:0]+8'H67;
else if(q[ 3:0]== 4'H9) q[15:0]=q[15:0]+4'H7;
else q[15:0]=q[15:0]+1; 
end


_7seg UUT0(.hex((q[3:0])),
               .seg(segout0));
               
    _7seg UUT1(.hex((q[7:4])),
               .seg(segout1));           
               
    _7seg UUT2(.hex((q[11:8])),
               .seg(segout2));
               
    _7seg UUT3(.hex((q[15:12])),
               .seg(segout3));   
               
    assign HEX0=segout0[6:0];
    assign HEX1=segout1[6:0];     
    assign HEX2=segout2[6:0];
    assign HEX3=segout3[6:0];   
                             

endmodule

//=======================================
//=======================================
//Clock input 50MHZ
//=======================================
 module _1HZ (CLK, RSTn, LED_Out);

    input CLK;
    input RSTn;
    output LED_Out;
    
    /*************************************/
    
    parameter T1S = 26'd50_000_000;  //50MHZ 
    
    /*************************************/
    
    reg [25:0]Count1;
    
    always @ ( posedge CLK or negedge RSTn )
    begin
     if( !RSTn ) 
         Count1 <= 26'd0;
     else if( Count1 == T1S )
         Count1 <= 26'd0;
     else
         Count1 <= Count1 + 1'b1;
end        
 /*************************************/
reg rLED_Out;
 always @ ( posedge CLK or negedge RSTn )
    begin
        if( !RSTn ) 
            rLED_Out <= 1'b0;
        else if( Count1 >= 26'd0 && Count1 < 26'd25_000_000 )
          //0.5sec ON , o.5sec OFF
            rLED_Out <= 1'b1;
        else 
            rLED_Out <= 1'b0;
     end  
          
     /***************************************/
     
     assign LED_Out = rLED_Out;
     
     /***************************************/
              
    
endmodule


//-----------------------------------------
//Common-cathod seven segment display
//using case.....endcase statement
//Filename : sevenseg_case.v
//----------------------------------------- 
module _7seg(hex , seg);
    input  [3:0] hex;
    output [7:0] seg;
    reg    [7:0] seg;
    
        

// segment encoding
//      0
//     ---  
//  5 |   | 1
//     ---   <- 6
//  4 |   | 2
//     ---
//      3
always @(hex)
begin
case (hex)
       // Dot point is always disable
       4'b0001 : seg = 8'b11111001;   //1 = F9H
       4'b0010 : seg = 8'b10100100;   //2 = A4H
       4'b0011 : seg = 8'b10110000;   //3 = B0H
       4'b0100 : seg = 8'b10011001;   //4 = 99H
       4'b0101 : seg = 8'b10010010;   //5 = 92H
       4'b0110 : seg = 8'b10000010;   //6 = 82H
       4'b0111 : seg = 8'b11111000;   //7 = F8H
       4'b1000 : seg = 8'b10000000;   //8 = 80H
       4'b1001 : seg = 8'b10010000;   //9 = 90H
       4'b1010 : seg = 8'b10001000;   //A = 88H
       4'b1011 : seg = 8'b10000011;   //b = 83H
       4'b1100 : seg = 8'b11000110;   //C = C6H
       4'b1101 : seg = 8'b10100001;   //d = A1H
       4'b1110 : seg = 8'b10000110;   //E = 86H
       4'b1111 : seg = 8'b10001110;   //F = 8EH
       default : seg = 8'b11000000;   //0 = C0H
     endcase
   end
   
endmodule

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