Verilog HDL: Switch-level Modeling

源自http://asic-soc.blogspot.tw/2012/06/verilog-hdl-switch-level-modeling.html

Verilog HDL: Switch-level Modeling

Mos  switch  keywords :

->nmos(output,data,control)

->pmos(output,data,control)

->cmos(output,data,ncontrol,pcontrol);          

   

Bidirectional  switch  keywords :

->trans (inout1,inout2);

->tranif0(inout1,inout2,control);

->tranif1(inout1,inout2,control);

Power  and  Ground  Keywords :

->supply1     //vdd

->supply0     //vss  or  GND

Resistive  Switch  Keywords :

->rnmos       //resistive  nmos

->rpmos       //resistive  pmos

->rcmos

->rtrans

->rtranif0

->rtranif1

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