月考類型

1) 請將下列程式輸出結果 寫出來

module sim_test ;
integer s,t;
initial begin 
s=4 ;
t=6;
forever begin 
#5 s=t+s ;
#5 t=s-1;
end
end

initial #40 $finish ;

initial begin 
$monitor ($time , "s = %d t = %d " ,s , t );
end

endmodule

請將下列程式輸出結果 寫出來

•ex. a = 4’b0011; b = 4’b1101;
      ~a      = _______;
      a&b  = ________;

      a^b    =  _______;

      a~^b  =  _______; 

請將下列程式輸出結果 寫出來

1 // Structural model of AND gate from two NANDS 2 module and_from_nand(); 3 4 reg X, Y; 5 wire F, W; 6 // Two instantiations of the module NAND 7 nand U1(W,X, Y); 8 nand U2(F, W, W); 9 10 // Testbench Code 11 initial begin 12 $monitor ("X = %b Y = %b F = %b", X, Y, F); 13 X = 0; 14 Y = 0; 15 #1 X = 1; 16 #1 Y = 1; 17 #1 X = 0; 18 #1 $finish; 19 end 20 21 endmodule

2) 寫出下列Gate Level Verilog 程式

3). 完成下列2對1 mux 程式

第20行指令

7 module mux_using_assign( 8 din_0 , // Mux first input 9 din_1 , // Mux Second input 10 sel , // Select input 11 mux_out // Mux output 12 ); 13 //-----------Input Ports--------------- 14 input din_0, din_1, sel ; 15 //-----------Output Ports--------------- 16 output mux_out; 17 //------------Internal Variables-------- 18 wire mux_out; 19 //-------------Code Start----------------- 20 assign________________________ 21 22 endmodule //End Of Module mux 第8-11 及13行指令 1 module mux_from_gates (); 2 reg c0,c1,c2,c3,A,B; 3 wire Y; 4 //Invert the sel signals 5 not (a_inv, A); 6 not (b_inv, B); 7 // 3-input AND gate 8 and (y0, ); 9 and (y1, ); 10 and (y2, ); 11 and (y3, ); 12 13 or (Y, ); 14 15 // Testbench Code goes here 16 initial begin 17 $monitor ( 18 "c0 = %b c1 = %b c2 = %b c3 = %b A = %b B = %b Y = %b", 19 c0, c1, c2, c3, A, B, Y); 20 c0 = 0; 21 c1 = 0; 22 c2 = 0; 23 c3 = 0; 24 A = 0; 25 B = 0; 26 #1 A = 1; 27 #2 B = 1; 28 #4 A = 0; 29 #8 $finish; 30 end 31 32 always #1 c0 = ~c0; 33 always #2 c1 = ~c1; 34 always #3 c2 = ~c2; 35 always #4 c3 = ~c3; 36 37 endmodule

4).