Master-Slave D Flip-Flop Verilog Code

Master-Slave D Flip-Flop Verilog Code

//==========================================

//Master-Slave D Flip-Flop

`timescale 1ns/100ps

module RS_master_slave (SW,KEY, LEDR, LEDG);

input [17:0] SW; // toggle switches

input [3:0] KEY;                   //Push bottom    

output [17:0] LEDR; // red LEDs

output [7:0] LEDG; // green LEDs

   

    defparam master.tplh=4, master.tphl=4;

    defparam slave.tplh=4, slave.tphl=4;

wire d,c;

wire q,q_b;

wire qm, qm_b;

    

    

assign LEDR = SW;

assign d = SW[0];      //set Data input

assign c = KEY[0];    //set Clock 

    latch_p  

      master ( d, ~d, c, qm, qm_b ),

      slave  ( qm, qm_b, ~c, q, q_b );

     

assign LEDG[0]=q;

assign LEDG[1]=q_b;

endmodule

/*  

Master-Slave D Flip-Flop Verilog Code

`timescale 1ns/100ps

module master_slave (input d, c, output q, q_b );

   wire qm, qm_b;

   defparam master.tplh=4, master.tphl=4, slave.tplh=4, slave.tphl=4;

   

   latch_p  

      master ( d, ~d, c, qm, qm_b ),

      slave  ( qm, qm_b, ~c, q, q_b );

endmodule

*/

//==========================================

`timescale 1ns/100ps

module latch_p (s,r,c,q,q_b);  //(input s, r, c, output q, q_b );

input s,r,c;  

output q,q_b;  

       parameter tplh=3, tphl=5 ;

   

wire _s, _r;

nand #(tplh,tphl) 

             g1 ( _s, s, c ),

             g2 ( _r, r, c ),

            g3 ( q, _s, q_b ),

            g4 ( q_b, _r, q );        

endmodule

/*

`timescale 1ns/100ps

module latch_p #(parameter tplh=3, tphl=5) 

   (input s, r, c, output q, q_b );

   wire _s, _r;

   nand #(tplh,tphl) 

      g1 ( _s, s, c ),

      g2 ( _r, r, c ),

      g3 ( q, _s, q_b ),

      g4 ( q_b, _r, q );    

endmodule

*/

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