P4-26 Home work 參考用

P4-26 Home work1  沒有Modelsim 自行設計Testbench program

//Verilog for Modelsim model

//P4-26 Home Work 1

`timescale 1us/1us

module hm1 (

input  [2:0] Din,

output [7:0] Y

);

wire d0_n,d1_n,d2_n;

not(d0_n,Din[0]);  //D0_bar 

not(d1_n,Din[1]);  //D1_bar

not(d2_n,Din[2]);  //D2_bar

or (Y[0],Din[2],Din[1],Din[0]);  //Y0 =  D2 + D1  + D0 

or (Y[1],Din[2],Din[1],d0_n  );  //Y1 =  D2 + D1  + /D0

or (Y[2],Din[2],D1_n  ,Din[0]);  //Y2 =  D2 + /D1 + D0

or (Y[3],Din[2],d1_n  ,D0_n  );  //Y3 =  D2 + /D1 + /D0

or (Y[4],D2_n  ,Din[1],Din[0]);  //Y4 =  /D2 + D1 + D0

or (Y[5],D2_n  ,Din[1],D0_n  );  //Y5 =  /D2 + D1 + /D0

or (Y[6],D2_n  ,D1_n  ,Din[0]);  //Y6 =  /D2 + /D1 + D0

or (Y[7],D2_n  ,D1_n  ,D0_n  );  //Y7 =  /D2 + /D1 + /D0

endmodule

  

P4-26 Home work2  沒有Modelsim 自行設計Testbench program

//Verilog for Modelsim model
//P4-26 Home Work 2
`timescale 1us/1us
module hm2 (input din, c, output q, q_b );
   
   wire _s, _r;

   not(din_n,din);  //s_bar
     
   nand  
      g1 ( _s, din, c ),
      g2 ( _r, din_n, c ),
      g3 ( q, _s, q_b ),
      g4 ( q_b, _r, q );    
endmodule




P4-26 Home work4  沒有Modelsim 自行設計Testbench program

//Verilog for Modelsim model

//P4-26 Home Work 4

`timescale 1us/1us

module hm4(din,s,y);

input din,s;

output [1:0]y;

wire s0 ;

not(s_n,s);

and(y[0],din,s_n);

and(y[1],din,s);

endmodule

P4-26 Home work7  沒有Modelsim 自行設計Testbench program

//Description of 4-bit adder 

module _4bit_adder (S,C4,A,B,C0);

  input [3:0] A,B;

  input C0;

  output [3:0] S; 

  output C4;

  wire C1,C2,C3;  //Intermediate carries

//Instantiate the fulladder 

  fulladder  FA0 (S[0],C1,A[0],B[0],C0),

             FA1 (S[1],C2,A[1],B[1],C1),

             FA2 (S[2],C3,A[2],B[2],C2), 

             FA3 (S[3],C4,A[3],B[3],C3);

endmodule

//Description of full adder  

module fulladder (S,C,x,y,z);

  input x,y,z;

  output S,C;

  wire S1,D1,D2; //Outputs of first XOR and two AND gates 

//Instantiate the halfadder 

   halfadder HA1 (S1,D1,x,y), 

             HA2 (S,D2,S1,z);

   or g1(C,D2,D1);

endmodule

//Gate-level hierarchical description of 4-bit adder 

// Description of half adder  

module halfadder (S,C,x,y);

  input x,y;

  output S,C;

//Instantiate primitive gates

  xor (S,x,y);

  and (C,x,y);

endmodule