P4-24 4對1多工器Verilog 程式 改寫成De2-70 實驗版適用

P4-24 4對1多工器Verilog 程式

module mux1x4 (SW, LEDR, LEDG);
input [17:0] SW; // toggle switches
output [17:0] LEDR; // red  LEDS   
  output [7:0] LEDG; // green LEDs
  
//set original program input , output 
wire y;
wire [1:0] s;     //Select signal
wire [3:0] i;
   
   
    //mapping to hardware 
    assign LEDR = SW;
    //assing input to SW
    assign i=SW[3:0];
    assign s=SW[9:8];
        
    bufif0 (y0, i[0], s[0]);
bufif1 (y0, i[1], s[0]);
bufif0 (y1, i[2], s[0]);
bufif1 (y1, i[3], s[0]);
bufif0 (y, y0, s[1]);
bufif1 (y, y1, s[1]);
    
assign LEDG[0]=y;

endmodule




/*
module mux4_1b_g(y, s, i);

// Port Declarations
output y;  //output y
input [1:0] s; // Data in : a, b;  Select: s
input [3:0] i;

//Internal signal declarations
wire y0, y1;

// Instantiates buffers
bufif0 (y0, i[0], s[0]);
bufif1 (y0, i[1], s[0]);
bufif0 (y1, i[2], s[0]);
bufif1 (y1, i[3], s[0]);
bufif0 (y, y0, s[1]);
bufif1 (y, y1, s[1]);
endmodule
*/