Dataflow Modeling

http://only-vlsi.blogspot.tw/2008/01/dataflow-modeling.html

Dataflow Modeling

>> Introduction
>> The assign Statement
>> Delays
>> Examples


Introduction

Dataflow modeling is a higher level of abstraction. The designer no need have any knowledge of logic circuit. He should be aware of data flow of the design. The gate level modeling becomes very complex for a VLSI circuit. Hence dataflow modeling became a very important way of implementing the design.
In dataflow modeling most of the design is implemented using continuous assignments, which are used to drive a value onto a net. The continuous assignments are made using the keyword assign.

The assign statement

The assign statement is used to make continuous assignment in the dataflow modeling. The assign statement usage is given below:

assign out = in0 + in1; // in0 + in1 is evaluated and then assigned to out.

Note:

• The LHS of assign statement must always be a scalar or vector net or a concatenation. It cannot be a register.
• Continuous statements are always active statements.
• Registers or nets or function calls can come in the RHS of the assignment.
• The RHS expression is evaluated whenever one of its operands changes. Then the result is assigned to the LHS.
• Delays can be specified.

Examples:

assign out[3:0] = in0[3:0] & in1[3:0];

assign {o3, o2, o1, o0} = in0[3:0] | {in1[2:0],in2}; // Use of concatenation.

Implicit Net Declaration:

wire in0, in1;
assign out = in0 ^ in1;

In the above example out is undeclared, but verilog makes an implicit net declaration for out.

Implicit Continuous Assignment:

wire out = in0 ^ in1;

The above line is the implicit continuous assignment. It is same as,

wire out;
assign out = in0 ^ in1;

Delays

There are three types of delays associated with dataflow modeling. They are: Normal/regular assignment delay, implicit continuous assignment delay and net declaration delay.

Normal/regular assignment delay:

assign #10 out = in0 | in1;

If there is any change in the operands in the RHS, then RHS expression will be evaluated after 10 units of time. Lets say that at time t, if there is change in one of the operands in the above example, then the expression is calculated at t+10 units of time. The value of RHS operands present at time t+10 is used to evaluate the expression.

Implicit continuous assignment delay:

wire #10 out = in0 ^ in1;

is same as

wire out;
assign 10 out = in0 ^ in1;

Net declaration delay:

wire #10 out;
assign out = in;

is same as

wire out;
assign #10 out = in;

Examples

1. Implementation of a 2x4 decoder.

module decoder_2x4 (out, in0, in1);

output out[0:3];
input in0, in1;

// Data flow modeling uses logic operators.
assign out[0:3] = { ~in0 & ~in1, in0 & ~in1,
                  ~in0 & in1, in0 & in1 };

endmodule

2. Implementation of a 4x1 multiplexer.

module mux_4x1 (out, in0, in1, in2, in3, s0, s1);

output out;
input in0, in1, in2, in3;
input s0, s1;

assign out = (~s0 & ~s1 & in0)|(s0 & ~s1 & in1)|
             (~s0 & s1 & in2)|(s0 & s1 & in0);

endmodule

3. Implementation of a 8x1 multiplexer using 4x1 multiplexers.

module mux_8x1 (out, in, sel);

output out;
input [7:0] in;
input [2:0] sel;

wire m1, m2;

// Instances of 4x1 multiplexers.
mux_4x1 mux_1 (m1, in[0], in[1], in[2],
               in[3], sel[0], sel[1]);
mux_4x1 mux_2 (m2, in[4], in[5], in[6],
               in[7], sel[0], sel[1]);

assign out = (~sel[2] & m1)|(sel[2] & m2);

endmodule

4. Implementation of a Full adder.

module full_adder (sum, c_out, in0, in1, c_in);

output sum, c_out;
input in0, in1, c_in;

assign { c_out, sum } = in0 + in1 + c_in;

endmodule