//test bench//
`timescale 1 ns/1 ps
module odd_tb();
reg [15:0]din;
wire odd_parity;
odd_parity_16 uut (.din(din),
.odd_parity16(odd_parity));
initial
begin
$display("time,\t din,\t parity ");
$monitor("%g,\t %b,\t %b",$time,din,odd_parity);
din=16'd0;
#10 din=16'd10;
#20 din=16'd20;
#30 din=16'd21;
#40 din=16'd255;
#50 din=16'd254;
#60 din=16'd221;
#70 din=16'd198;
#80 din=16'd65535;
#90 din=16'd65534;
end
initial
#500 $stop;
endmodule
//=====================================
//check odd parity
//filename : odd_parity_16.v
`timescale 1 ns/1 ps
module odd_parity_16( din,odd_parity16);
output odd_parity16;
input [15:0] din;
wire odd_parity1,odd_parity2;
odd_parity_8 uut1 (.din(din[7:0]),
.odd_parity8(odd_parity1));
odd_parity_8 uut2 (.din(din[15:8]),
.odd_parity8(odd_parity2));
assign odd_parity16 =odd_parity1^odd_parity2;
endmodule
//=============================================
//check odd parity
//filename : odd_parity_8.v
`timescale 1 ns/1 ps
module odd_parity_8( din,odd_parity8);
output odd_parity8;
input [7:0] din;
assign odd_parity8 = ^ din;
endmodule
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